1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2011 Cavium Networks 7 * Copyright (C) 2008 Wind River Systems 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/init.h> 12 #include <linux/irq.h> 13 #include <linux/i2c.h> 14 #include <linux/usb.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/etherdevice.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/slab.h> 20 #include <linux/platform_device.h> 21 #include <linux/of_platform.h> 22 #include <linux/of_fdt.h> 23 #include <linux/libfdt.h> 24 #include <linux/usb/ehci_pdriver.h> 25 #include <linux/usb/ohci_pdriver.h> 26 27 #include <asm/octeon/octeon.h> 28 #include <asm/octeon/cvmx-rnm-defs.h> 29 #include <asm/octeon/cvmx-helper.h> 30 #include <asm/octeon/cvmx-helper-board.h> 31 #include <asm/octeon/cvmx-uctlx-defs.h> 32 33 /* Octeon Random Number Generator. */ 34 static int __init octeon_rng_device_init(void) 35 { 36 struct platform_device *pd; 37 int ret = 0; 38 39 struct resource rng_resources[] = { 40 { 41 .flags = IORESOURCE_MEM, 42 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), 43 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf 44 }, { 45 .flags = IORESOURCE_MEM, 46 .start = cvmx_build_io_address(8, 0), 47 .end = cvmx_build_io_address(8, 0) + 0x7 48 } 49 }; 50 51 pd = platform_device_alloc("octeon_rng", -1); 52 if (!pd) { 53 ret = -ENOMEM; 54 goto out; 55 } 56 57 ret = platform_device_add_resources(pd, rng_resources, 58 ARRAY_SIZE(rng_resources)); 59 if (ret) 60 goto fail; 61 62 ret = platform_device_add(pd); 63 if (ret) 64 goto fail; 65 66 return ret; 67 fail: 68 platform_device_put(pd); 69 70 out: 71 return ret; 72 } 73 device_initcall(octeon_rng_device_init); 74 75 #ifdef CONFIG_USB 76 77 static DEFINE_MUTEX(octeon2_usb_clocks_mutex); 78 79 static int octeon2_usb_clock_start_cnt; 80 81 static void octeon2_usb_clocks_start(struct device *dev) 82 { 83 u64 div; 84 union cvmx_uctlx_if_ena if_ena; 85 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; 86 union cvmx_uctlx_uphy_ctl_status uphy_ctl_status; 87 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status; 88 int i; 89 unsigned long io_clk_64_to_ns; 90 u32 clock_rate = 12000000; 91 bool is_crystal_clock = false; 92 93 94 mutex_lock(&octeon2_usb_clocks_mutex); 95 96 octeon2_usb_clock_start_cnt++; 97 if (octeon2_usb_clock_start_cnt != 1) 98 goto exit; 99 100 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate(); 101 102 if (dev->of_node) { 103 struct device_node *uctl_node; 104 const char *clock_type; 105 106 uctl_node = of_get_parent(dev->of_node); 107 if (!uctl_node) { 108 dev_err(dev, "No UCTL device node\n"); 109 goto exit; 110 } 111 i = of_property_read_u32(uctl_node, 112 "refclk-frequency", &clock_rate); 113 if (i) { 114 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); 115 goto exit; 116 } 117 i = of_property_read_string(uctl_node, 118 "refclk-type", &clock_type); 119 120 if (!i && strcmp("crystal", clock_type) == 0) 121 is_crystal_clock = true; 122 } 123 124 /* 125 * Step 1: Wait for voltages stable. That surely happened 126 * before starting the kernel. 127 * 128 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1 129 */ 130 if_ena.u64 = 0; 131 if_ena.s.en = 1; 132 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); 133 134 /* Step 3: Configure the reference clock, PHY, and HCLK */ 135 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); 136 137 /* 138 * If the UCTL looks like it has already been started, skip 139 * the initialization, otherwise bus errors are obtained. 140 */ 141 if (clk_rst_ctl.s.hrst) 142 goto end_clock; 143 /* 3a */ 144 clk_rst_ctl.s.p_por = 1; 145 clk_rst_ctl.s.hrst = 0; 146 clk_rst_ctl.s.p_prst = 0; 147 clk_rst_ctl.s.h_clkdiv_rst = 0; 148 clk_rst_ctl.s.o_clkdiv_rst = 0; 149 clk_rst_ctl.s.h_clkdiv_en = 0; 150 clk_rst_ctl.s.o_clkdiv_en = 0; 151 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 152 153 /* 3b */ 154 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1; 155 switch (clock_rate) { 156 default: 157 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n", 158 clock_rate); 159 /* Fall through */ 160 case 12000000: 161 clk_rst_ctl.s.p_refclk_div = 0; 162 break; 163 case 24000000: 164 clk_rst_ctl.s.p_refclk_div = 1; 165 break; 166 case 48000000: 167 clk_rst_ctl.s.p_refclk_div = 2; 168 break; 169 } 170 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 171 172 /* 3c */ 173 div = octeon_get_io_clock_rate() / 130000000ull; 174 175 switch (div) { 176 case 0: 177 div = 1; 178 break; 179 case 1: 180 case 2: 181 case 3: 182 case 4: 183 break; 184 case 5: 185 div = 4; 186 break; 187 case 6: 188 case 7: 189 div = 6; 190 break; 191 case 8: 192 case 9: 193 case 10: 194 case 11: 195 div = 8; 196 break; 197 default: 198 div = 12; 199 break; 200 } 201 clk_rst_ctl.s.h_div = div; 202 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 203 /* Read it back, */ 204 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); 205 clk_rst_ctl.s.h_clkdiv_en = 1; 206 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 207 /* 3d */ 208 clk_rst_ctl.s.h_clkdiv_rst = 1; 209 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 210 211 /* 3e: delay 64 io clocks */ 212 ndelay(io_clk_64_to_ns); 213 214 /* 215 * Step 4: Program the power-on reset field in the UCTL 216 * clock-reset-control register. 217 */ 218 clk_rst_ctl.s.p_por = 0; 219 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 220 221 /* Step 5: Wait 1 ms for the PHY clock to start. */ 222 mdelay(1); 223 224 /* 225 * Step 6: Program the reset input from automatic test 226 * equipment field in the UPHY CSR 227 */ 228 uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0)); 229 uphy_ctl_status.s.ate_reset = 1; 230 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64); 231 232 /* Step 7: Wait for at least 10ns. */ 233 ndelay(10); 234 235 /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */ 236 uphy_ctl_status.s.ate_reset = 0; 237 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64); 238 239 /* 240 * Step 9: Wait for at least 20ns for UPHY to output PHY clock 241 * signals and OHCI_CLK48 242 */ 243 ndelay(20); 244 245 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */ 246 /* 10a */ 247 clk_rst_ctl.s.o_clkdiv_rst = 1; 248 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 249 250 /* 10b */ 251 clk_rst_ctl.s.o_clkdiv_en = 1; 252 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 253 254 /* 10c */ 255 ndelay(io_clk_64_to_ns); 256 257 /* 258 * Step 11: Program the PHY reset field: 259 * UCTL0_CLK_RST_CTL[P_PRST] = 1 260 */ 261 clk_rst_ctl.s.p_prst = 1; 262 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 263 264 /* Step 12: Wait 1 uS. */ 265 udelay(1); 266 267 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */ 268 clk_rst_ctl.s.hrst = 1; 269 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 270 271 end_clock: 272 /* Now we can set some other registers. */ 273 274 for (i = 0; i <= 1; i++) { 275 port_ctl_status.u64 = 276 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); 277 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */ 278 port_ctl_status.s.txvreftune = 15; 279 port_ctl_status.s.txrisetune = 1; 280 port_ctl_status.s.txpreemphasistune = 1; 281 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), 282 port_ctl_status.u64); 283 } 284 285 /* Set uSOF cycle period to 60,000 bits. */ 286 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); 287 exit: 288 mutex_unlock(&octeon2_usb_clocks_mutex); 289 } 290 291 static void octeon2_usb_clocks_stop(void) 292 { 293 mutex_lock(&octeon2_usb_clocks_mutex); 294 octeon2_usb_clock_start_cnt--; 295 mutex_unlock(&octeon2_usb_clocks_mutex); 296 } 297 298 static int octeon_ehci_power_on(struct platform_device *pdev) 299 { 300 octeon2_usb_clocks_start(&pdev->dev); 301 return 0; 302 } 303 304 static void octeon_ehci_power_off(struct platform_device *pdev) 305 { 306 octeon2_usb_clocks_stop(); 307 } 308 309 static struct usb_ehci_pdata octeon_ehci_pdata = { 310 /* Octeon EHCI matches CPU endianness. */ 311 #ifdef __BIG_ENDIAN 312 .big_endian_mmio = 1, 313 #endif 314 .dma_mask_64 = 1, 315 .power_on = octeon_ehci_power_on, 316 .power_off = octeon_ehci_power_off, 317 }; 318 319 static void __init octeon_ehci_hw_start(struct device *dev) 320 { 321 union cvmx_uctlx_ehci_ctl ehci_ctl; 322 323 octeon2_usb_clocks_start(dev); 324 325 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); 326 /* Use 64-bit addressing. */ 327 ehci_ctl.s.ehci_64b_addr_en = 1; 328 ehci_ctl.s.l2c_addr_msb = 0; 329 #ifdef __BIG_ENDIAN 330 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 331 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 332 #else 333 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ 334 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ 335 ehci_ctl.s.inv_reg_a2 = 1; 336 #endif 337 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); 338 339 octeon2_usb_clocks_stop(); 340 } 341 342 static int __init octeon_ehci_device_init(void) 343 { 344 struct platform_device *pd; 345 struct device_node *ehci_node; 346 int ret = 0; 347 348 ehci_node = of_find_node_by_name(NULL, "ehci"); 349 if (!ehci_node) 350 return 0; 351 352 pd = of_find_device_by_node(ehci_node); 353 if (!pd) 354 return 0; 355 356 pd->dev.platform_data = &octeon_ehci_pdata; 357 octeon_ehci_hw_start(&pd->dev); 358 359 return ret; 360 } 361 device_initcall(octeon_ehci_device_init); 362 363 static int octeon_ohci_power_on(struct platform_device *pdev) 364 { 365 octeon2_usb_clocks_start(&pdev->dev); 366 return 0; 367 } 368 369 static void octeon_ohci_power_off(struct platform_device *pdev) 370 { 371 octeon2_usb_clocks_stop(); 372 } 373 374 static struct usb_ohci_pdata octeon_ohci_pdata = { 375 /* Octeon OHCI matches CPU endianness. */ 376 #ifdef __BIG_ENDIAN 377 .big_endian_mmio = 1, 378 #endif 379 .power_on = octeon_ohci_power_on, 380 .power_off = octeon_ohci_power_off, 381 }; 382 383 static void __init octeon_ohci_hw_start(struct device *dev) 384 { 385 union cvmx_uctlx_ohci_ctl ohci_ctl; 386 387 octeon2_usb_clocks_start(dev); 388 389 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); 390 ohci_ctl.s.l2c_addr_msb = 0; 391 #ifdef __BIG_ENDIAN 392 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 393 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 394 #else 395 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ 396 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ 397 ohci_ctl.s.inv_reg_a2 = 1; 398 #endif 399 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); 400 401 octeon2_usb_clocks_stop(); 402 } 403 404 static int __init octeon_ohci_device_init(void) 405 { 406 struct platform_device *pd; 407 struct device_node *ohci_node; 408 int ret = 0; 409 410 ohci_node = of_find_node_by_name(NULL, "ohci"); 411 if (!ohci_node) 412 return 0; 413 414 pd = of_find_device_by_node(ohci_node); 415 if (!pd) 416 return 0; 417 418 pd->dev.platform_data = &octeon_ohci_pdata; 419 octeon_ohci_hw_start(&pd->dev); 420 421 return ret; 422 } 423 device_initcall(octeon_ohci_device_init); 424 425 #endif /* CONFIG_USB */ 426 427 428 static struct of_device_id __initdata octeon_ids[] = { 429 { .compatible = "simple-bus", }, 430 { .compatible = "cavium,octeon-6335-uctl", }, 431 { .compatible = "cavium,octeon-5750-usbn", }, 432 { .compatible = "cavium,octeon-3860-bootbus", }, 433 { .compatible = "cavium,mdio-mux", }, 434 { .compatible = "gpio-leds", }, 435 {}, 436 }; 437 438 static bool __init octeon_has_88e1145(void) 439 { 440 return !OCTEON_IS_MODEL(OCTEON_CN52XX) && 441 !OCTEON_IS_MODEL(OCTEON_CN6XXX) && 442 !OCTEON_IS_MODEL(OCTEON_CN56XX); 443 } 444 445 static void __init octeon_fdt_set_phy(int eth, int phy_addr) 446 { 447 const __be32 *phy_handle; 448 const __be32 *alt_phy_handle; 449 const __be32 *reg; 450 u32 phandle; 451 int phy; 452 int alt_phy; 453 const char *p; 454 int current_len; 455 char new_name[20]; 456 457 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); 458 if (!phy_handle) 459 return; 460 461 phandle = be32_to_cpup(phy_handle); 462 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); 463 464 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); 465 if (alt_phy_handle) { 466 u32 alt_phandle = be32_to_cpup(alt_phy_handle); 467 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); 468 } else { 469 alt_phy = -1; 470 } 471 472 if (phy_addr < 0 || phy < 0) { 473 /* Delete the PHY things */ 474 fdt_nop_property(initial_boot_params, eth, "phy-handle"); 475 /* This one may fail */ 476 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); 477 if (phy >= 0) 478 fdt_nop_node(initial_boot_params, phy); 479 if (alt_phy >= 0) 480 fdt_nop_node(initial_boot_params, alt_phy); 481 return; 482 } 483 484 if (phy_addr >= 256 && alt_phy > 0) { 485 const struct fdt_property *phy_prop; 486 struct fdt_property *alt_prop; 487 u32 phy_handle_name; 488 489 /* Use the alt phy node instead.*/ 490 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); 491 phy_handle_name = phy_prop->nameoff; 492 fdt_nop_node(initial_boot_params, phy); 493 fdt_nop_property(initial_boot_params, eth, "phy-handle"); 494 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); 495 alt_prop->nameoff = phy_handle_name; 496 phy = alt_phy; 497 } 498 499 phy_addr &= 0xff; 500 501 if (octeon_has_88e1145()) { 502 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); 503 memset(new_name, 0, sizeof(new_name)); 504 strcpy(new_name, "marvell,88e1145"); 505 p = fdt_getprop(initial_boot_params, phy, "compatible", 506 ¤t_len); 507 if (p && current_len >= strlen(new_name)) 508 fdt_setprop_inplace(initial_boot_params, phy, 509 "compatible", new_name, current_len); 510 } 511 512 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); 513 if (phy_addr == be32_to_cpup(reg)) 514 return; 515 516 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); 517 518 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); 519 520 p = fdt_get_name(initial_boot_params, phy, ¤t_len); 521 if (p && current_len == strlen(new_name)) 522 fdt_set_name(initial_boot_params, phy, new_name); 523 else 524 pr_err("Error: could not rename ethernet phy: <%s>", p); 525 } 526 527 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) 528 { 529 const u8 *old_mac; 530 int old_len; 531 u8 new_mac[6]; 532 u64 mac = *pmac; 533 int r; 534 535 old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address", 536 &old_len); 537 if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac)) 538 return; 539 540 new_mac[0] = (mac >> 40) & 0xff; 541 new_mac[1] = (mac >> 32) & 0xff; 542 new_mac[2] = (mac >> 24) & 0xff; 543 new_mac[3] = (mac >> 16) & 0xff; 544 new_mac[4] = (mac >> 8) & 0xff; 545 new_mac[5] = mac & 0xff; 546 547 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", 548 new_mac, sizeof(new_mac)); 549 550 if (r) { 551 pr_err("Setting \"local-mac-address\" failed %d", r); 552 return; 553 } 554 *pmac = mac + 1; 555 } 556 557 static void __init octeon_fdt_rm_ethernet(int node) 558 { 559 const __be32 *phy_handle; 560 561 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); 562 if (phy_handle) { 563 u32 ph = be32_to_cpup(phy_handle); 564 int p = fdt_node_offset_by_phandle(initial_boot_params, ph); 565 if (p >= 0) 566 fdt_nop_node(initial_boot_params, p); 567 } 568 fdt_nop_node(initial_boot_params, node); 569 } 570 571 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max) 572 { 573 char name_buffer[20]; 574 int eth; 575 int phy_addr; 576 int ipd_port; 577 578 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); 579 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); 580 if (eth < 0) 581 return; 582 if (p > max) { 583 pr_debug("Deleting port %x:%x\n", i, p); 584 octeon_fdt_rm_ethernet(eth); 585 return; 586 } 587 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 588 ipd_port = (0x100 * i) + (0x10 * p) + 0x800; 589 else 590 ipd_port = 16 * i + p; 591 592 phy_addr = cvmx_helper_board_get_mii_address(ipd_port); 593 octeon_fdt_set_phy(eth, phy_addr); 594 } 595 596 static void __init octeon_fdt_pip_iface(int pip, int idx) 597 { 598 char name_buffer[20]; 599 int iface; 600 int p; 601 int count = 0; 602 603 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); 604 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); 605 if (iface < 0) 606 return; 607 608 if (cvmx_helper_interface_enumerate(idx) == 0) 609 count = cvmx_helper_ports_on_interface(idx); 610 611 for (p = 0; p < 16; p++) 612 octeon_fdt_pip_port(iface, idx, p, count - 1); 613 } 614 615 void __init octeon_fill_mac_addresses(void) 616 { 617 const char *alias_prop; 618 char name_buffer[20]; 619 u64 mac_addr_base; 620 int aliases; 621 int pip; 622 int i; 623 624 aliases = fdt_path_offset(initial_boot_params, "/aliases"); 625 if (aliases < 0) 626 return; 627 628 mac_addr_base = 629 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | 630 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | 631 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | 632 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | 633 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | 634 (octeon_bootinfo->mac_addr_base[5] & 0xffull); 635 636 for (i = 0; i < 2; i++) { 637 int mgmt; 638 639 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i); 640 alias_prop = fdt_getprop(initial_boot_params, aliases, 641 name_buffer, NULL); 642 if (!alias_prop) 643 continue; 644 mgmt = fdt_path_offset(initial_boot_params, alias_prop); 645 if (mgmt < 0) 646 continue; 647 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); 648 } 649 650 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 651 if (!alias_prop) 652 return; 653 654 pip = fdt_path_offset(initial_boot_params, alias_prop); 655 if (pip < 0) 656 return; 657 658 for (i = 0; i <= 4; i++) { 659 int iface; 660 int p; 661 662 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i); 663 iface = fdt_subnode_offset(initial_boot_params, pip, 664 name_buffer); 665 if (iface < 0) 666 continue; 667 for (p = 0; p < 16; p++) { 668 int eth; 669 670 snprintf(name_buffer, sizeof(name_buffer), 671 "ethernet@%x", p); 672 eth = fdt_subnode_offset(initial_boot_params, iface, 673 name_buffer); 674 if (eth < 0) 675 continue; 676 octeon_fdt_set_mac_addr(eth, &mac_addr_base); 677 } 678 } 679 } 680 681 int __init octeon_prune_device_tree(void) 682 { 683 int i, max_port, uart_mask; 684 const char *pip_path; 685 const char *alias_prop; 686 char name_buffer[20]; 687 int aliases; 688 689 if (fdt_check_header(initial_boot_params)) 690 panic("Corrupt Device Tree."); 691 692 aliases = fdt_path_offset(initial_boot_params, "/aliases"); 693 if (aliases < 0) { 694 pr_err("Error: No /aliases node in device tree."); 695 return -EINVAL; 696 } 697 698 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) 699 max_port = 2; 700 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) 701 max_port = 1; 702 else 703 max_port = 0; 704 705 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) 706 max_port = 0; 707 708 for (i = 0; i < 2; i++) { 709 int mgmt; 710 snprintf(name_buffer, sizeof(name_buffer), 711 "mix%d", i); 712 alias_prop = fdt_getprop(initial_boot_params, aliases, 713 name_buffer, NULL); 714 if (alias_prop) { 715 mgmt = fdt_path_offset(initial_boot_params, alias_prop); 716 if (mgmt < 0) 717 continue; 718 if (i >= max_port) { 719 pr_debug("Deleting mix%d\n", i); 720 octeon_fdt_rm_ethernet(mgmt); 721 fdt_nop_property(initial_boot_params, aliases, 722 name_buffer); 723 } else { 724 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); 725 octeon_fdt_set_phy(mgmt, phy_addr); 726 } 727 } 728 } 729 730 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 731 if (pip_path) { 732 int pip = fdt_path_offset(initial_boot_params, pip_path); 733 if (pip >= 0) 734 for (i = 0; i <= 4; i++) 735 octeon_fdt_pip_iface(pip, i); 736 } 737 738 /* I2C */ 739 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || 740 OCTEON_IS_MODEL(OCTEON_CN63XX) || 741 OCTEON_IS_MODEL(OCTEON_CN68XX) || 742 OCTEON_IS_MODEL(OCTEON_CN56XX)) 743 max_port = 2; 744 else 745 max_port = 1; 746 747 for (i = 0; i < 2; i++) { 748 int i2c; 749 snprintf(name_buffer, sizeof(name_buffer), 750 "twsi%d", i); 751 alias_prop = fdt_getprop(initial_boot_params, aliases, 752 name_buffer, NULL); 753 754 if (alias_prop) { 755 i2c = fdt_path_offset(initial_boot_params, alias_prop); 756 if (i2c < 0) 757 continue; 758 if (i >= max_port) { 759 pr_debug("Deleting twsi%d\n", i); 760 fdt_nop_node(initial_boot_params, i2c); 761 fdt_nop_property(initial_boot_params, aliases, 762 name_buffer); 763 } 764 } 765 } 766 767 /* SMI/MDIO */ 768 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 769 max_port = 4; 770 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || 771 OCTEON_IS_MODEL(OCTEON_CN63XX) || 772 OCTEON_IS_MODEL(OCTEON_CN56XX)) 773 max_port = 2; 774 else 775 max_port = 1; 776 777 for (i = 0; i < 2; i++) { 778 int i2c; 779 snprintf(name_buffer, sizeof(name_buffer), 780 "smi%d", i); 781 alias_prop = fdt_getprop(initial_boot_params, aliases, 782 name_buffer, NULL); 783 784 if (alias_prop) { 785 i2c = fdt_path_offset(initial_boot_params, alias_prop); 786 if (i2c < 0) 787 continue; 788 if (i >= max_port) { 789 pr_debug("Deleting smi%d\n", i); 790 fdt_nop_node(initial_boot_params, i2c); 791 fdt_nop_property(initial_boot_params, aliases, 792 name_buffer); 793 } 794 } 795 } 796 797 /* Serial */ 798 uart_mask = 3; 799 800 /* Right now CN52XX is the only chip with a third uart */ 801 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) 802 uart_mask |= 4; /* uart2 */ 803 804 for (i = 0; i < 3; i++) { 805 int uart; 806 snprintf(name_buffer, sizeof(name_buffer), 807 "uart%d", i); 808 alias_prop = fdt_getprop(initial_boot_params, aliases, 809 name_buffer, NULL); 810 811 if (alias_prop) { 812 uart = fdt_path_offset(initial_boot_params, alias_prop); 813 if (uart_mask & (1 << i)) { 814 __be32 f; 815 816 f = cpu_to_be32(octeon_get_io_clock_rate()); 817 fdt_setprop_inplace(initial_boot_params, 818 uart, "clock-frequency", 819 &f, sizeof(f)); 820 continue; 821 } 822 pr_debug("Deleting uart%d\n", i); 823 fdt_nop_node(initial_boot_params, uart); 824 fdt_nop_property(initial_boot_params, aliases, 825 name_buffer); 826 } 827 } 828 829 /* Compact Flash */ 830 alias_prop = fdt_getprop(initial_boot_params, aliases, 831 "cf0", NULL); 832 if (alias_prop) { 833 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; 834 unsigned long base_ptr, region_base, region_size; 835 unsigned long region1_base = 0; 836 unsigned long region1_size = 0; 837 int cs, bootbus; 838 bool is_16bit = false; 839 bool is_true_ide = false; 840 __be32 new_reg[6]; 841 __be32 *ranges; 842 int len; 843 844 int cf = fdt_path_offset(initial_boot_params, alias_prop); 845 base_ptr = 0; 846 if (octeon_bootinfo->major_version == 1 847 && octeon_bootinfo->minor_version >= 1) { 848 if (octeon_bootinfo->compact_flash_common_base_addr) 849 base_ptr = octeon_bootinfo->compact_flash_common_base_addr; 850 } else { 851 base_ptr = 0x1d000800; 852 } 853 854 if (!base_ptr) 855 goto no_cf; 856 857 /* Find CS0 region. */ 858 for (cs = 0; cs < 8; cs++) { 859 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); 860 region_base = mio_boot_reg_cfg.s.base << 16; 861 region_size = (mio_boot_reg_cfg.s.size + 1) << 16; 862 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base 863 && base_ptr < region_base + region_size) { 864 is_16bit = mio_boot_reg_cfg.s.width; 865 break; 866 } 867 } 868 if (cs >= 7) { 869 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ 870 goto no_cf; 871 } 872 873 if (!(base_ptr & 0xfffful)) { 874 /* 875 * Boot loader signals availability of DMA (true_ide 876 * mode) by setting low order bits of base_ptr to 877 * zero. 878 */ 879 880 /* Asume that CS1 immediately follows. */ 881 mio_boot_reg_cfg.u64 = 882 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); 883 region1_base = mio_boot_reg_cfg.s.base << 16; 884 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; 885 if (!mio_boot_reg_cfg.s.en) 886 goto no_cf; 887 is_true_ide = true; 888 889 } else { 890 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); 891 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); 892 if (!is_16bit) { 893 __be32 width = cpu_to_be32(8); 894 fdt_setprop_inplace(initial_boot_params, cf, 895 "cavium,bus-width", &width, sizeof(width)); 896 } 897 } 898 new_reg[0] = cpu_to_be32(cs); 899 new_reg[1] = cpu_to_be32(0); 900 new_reg[2] = cpu_to_be32(0x10000); 901 new_reg[3] = cpu_to_be32(cs + 1); 902 new_reg[4] = cpu_to_be32(0); 903 new_reg[5] = cpu_to_be32(0x10000); 904 fdt_setprop_inplace(initial_boot_params, cf, 905 "reg", new_reg, sizeof(new_reg)); 906 907 bootbus = fdt_parent_offset(initial_boot_params, cf); 908 if (bootbus < 0) 909 goto no_cf; 910 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); 911 if (!ranges || len < (5 * 8 * sizeof(__be32))) 912 goto no_cf; 913 914 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); 915 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); 916 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); 917 if (is_true_ide) { 918 cs++; 919 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); 920 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); 921 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); 922 } 923 goto end_cf; 924 no_cf: 925 fdt_nop_node(initial_boot_params, cf); 926 927 end_cf: 928 ; 929 } 930 931 /* 8 char LED */ 932 alias_prop = fdt_getprop(initial_boot_params, aliases, 933 "led0", NULL); 934 if (alias_prop) { 935 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; 936 unsigned long base_ptr, region_base, region_size; 937 int cs, bootbus; 938 __be32 new_reg[6]; 939 __be32 *ranges; 940 int len; 941 int led = fdt_path_offset(initial_boot_params, alias_prop); 942 943 base_ptr = octeon_bootinfo->led_display_base_addr; 944 if (base_ptr == 0) 945 goto no_led; 946 /* Find CS0 region. */ 947 for (cs = 0; cs < 8; cs++) { 948 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); 949 region_base = mio_boot_reg_cfg.s.base << 16; 950 region_size = (mio_boot_reg_cfg.s.size + 1) << 16; 951 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base 952 && base_ptr < region_base + region_size) 953 break; 954 } 955 956 if (cs > 7) 957 goto no_led; 958 959 new_reg[0] = cpu_to_be32(cs); 960 new_reg[1] = cpu_to_be32(0x20); 961 new_reg[2] = cpu_to_be32(0x20); 962 new_reg[3] = cpu_to_be32(cs); 963 new_reg[4] = cpu_to_be32(0); 964 new_reg[5] = cpu_to_be32(0x20); 965 fdt_setprop_inplace(initial_boot_params, led, 966 "reg", new_reg, sizeof(new_reg)); 967 968 bootbus = fdt_parent_offset(initial_boot_params, led); 969 if (bootbus < 0) 970 goto no_led; 971 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); 972 if (!ranges || len < (5 * 8 * sizeof(__be32))) 973 goto no_led; 974 975 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); 976 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); 977 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); 978 goto end_led; 979 980 no_led: 981 fdt_nop_node(initial_boot_params, led); 982 end_led: 983 ; 984 } 985 986 /* OHCI/UHCI USB */ 987 alias_prop = fdt_getprop(initial_boot_params, aliases, 988 "uctl", NULL); 989 if (alias_prop) { 990 int uctl = fdt_path_offset(initial_boot_params, alias_prop); 991 992 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || 993 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { 994 pr_debug("Deleting uctl\n"); 995 fdt_nop_node(initial_boot_params, uctl); 996 fdt_nop_property(initial_boot_params, aliases, "uctl"); 997 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || 998 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { 999 /* Missing "refclk-type" defaults to crystal. */ 1000 fdt_nop_property(initial_boot_params, uctl, "refclk-type"); 1001 } 1002 } 1003 1004 /* DWC2 USB */ 1005 alias_prop = fdt_getprop(initial_boot_params, aliases, 1006 "usbn", NULL); 1007 if (alias_prop) { 1008 int usbn = fdt_path_offset(initial_boot_params, alias_prop); 1009 1010 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 || 1011 !octeon_has_feature(OCTEON_FEATURE_USB))) { 1012 pr_debug("Deleting usbn\n"); 1013 fdt_nop_node(initial_boot_params, usbn); 1014 fdt_nop_property(initial_boot_params, aliases, "usbn"); 1015 } else { 1016 __be32 new_f[1]; 1017 enum cvmx_helper_board_usb_clock_types c; 1018 c = __cvmx_helper_board_usb_get_clock_type(); 1019 switch (c) { 1020 case USB_CLOCK_TYPE_REF_48: 1021 new_f[0] = cpu_to_be32(48000000); 1022 fdt_setprop_inplace(initial_boot_params, usbn, 1023 "refclk-frequency", new_f, sizeof(new_f)); 1024 /* Fall through ...*/ 1025 case USB_CLOCK_TYPE_REF_12: 1026 /* Missing "refclk-type" defaults to external. */ 1027 fdt_nop_property(initial_boot_params, usbn, "refclk-type"); 1028 break; 1029 default: 1030 break; 1031 } 1032 } 1033 } 1034 1035 if (octeon_bootinfo->board_type != CVMX_BOARD_TYPE_CUST_DSR1000N) { 1036 int dsr1000n_leds = fdt_path_offset(initial_boot_params, 1037 "/dsr1000n-leds"); 1038 if (dsr1000n_leds >= 0) 1039 fdt_nop_node(initial_boot_params, dsr1000n_leds); 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int __init octeon_publish_devices(void) 1046 { 1047 return of_platform_bus_probe(NULL, octeon_ids, NULL); 1048 } 1049 device_initcall(octeon_publish_devices); 1050 1051 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); 1052 MODULE_LICENSE("GPL"); 1053 MODULE_DESCRIPTION("Platform driver for Octeon SOC"); 1054