xref: /linux/arch/mips/cavium-octeon/dma-octeon.c (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2000  Ani Joshi <ajoshi@unixbox.com>
7  * Copyright (C) 2000, 2001  Ralf Baechle <ralf@gnu.org>
8  * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
9  * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
10  * IP32 changes by Ilya.
11  * Copyright (C) 2010 Cavium Networks, Inc.
12  */
13 #include <linux/dma-mapping.h>
14 #include <linux/scatterlist.h>
15 #include <linux/bootmem.h>
16 #include <linux/export.h>
17 #include <linux/swiotlb.h>
18 #include <linux/types.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 
22 #include <asm/bootinfo.h>
23 
24 #include <asm/octeon/octeon.h>
25 
26 #ifdef CONFIG_PCI
27 #include <asm/octeon/pci-octeon.h>
28 #include <asm/octeon/cvmx-npi-defs.h>
29 #include <asm/octeon/cvmx-pci-defs.h>
30 
31 static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
32 {
33 	if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
34 		return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
35 	else
36 		return paddr;
37 }
38 
39 static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
40 {
41 	if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
42 		return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
43 	else
44 		return daddr;
45 }
46 
47 static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
48 {
49 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
50 		paddr -= 0x400000000ull;
51 	return octeon_hole_phys_to_dma(paddr);
52 }
53 
54 static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
55 {
56 	daddr = octeon_hole_dma_to_phys(daddr);
57 
58 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
59 		daddr += 0x400000000ull;
60 
61 	return daddr;
62 }
63 
64 static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
65 {
66 	return octeon_hole_phys_to_dma(paddr);
67 }
68 
69 static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
70 {
71 	return octeon_hole_dma_to_phys(daddr);
72 }
73 
74 static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
75 {
76 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
77 		paddr -= 0x400000000ull;
78 
79 	/* Anything in the BAR1 hole or above goes via BAR2 */
80 	if (paddr >= 0xf0000000ull)
81 		paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
82 
83 	return paddr;
84 }
85 
86 static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
87 {
88 	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
89 		daddr -= OCTEON_BAR2_PCI_ADDRESS;
90 
91 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
92 		daddr += 0x400000000ull;
93 	return daddr;
94 }
95 
96 static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
97 					   phys_addr_t paddr)
98 {
99 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
100 		paddr -= 0x400000000ull;
101 
102 	/* Anything not in the BAR1 range goes via BAR2 */
103 	if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
104 		paddr = paddr - octeon_bar1_pci_phys;
105 	else
106 		paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
107 
108 	return paddr;
109 }
110 
111 static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
112 					    dma_addr_t daddr)
113 {
114 	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
115 		daddr -= OCTEON_BAR2_PCI_ADDRESS;
116 	else
117 		daddr += octeon_bar1_pci_phys;
118 
119 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
120 		daddr += 0x400000000ull;
121 	return daddr;
122 }
123 
124 #endif /* CONFIG_PCI */
125 
126 static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
127 	unsigned long offset, size_t size, enum dma_data_direction direction,
128 	unsigned long attrs)
129 {
130 	dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
131 					    direction, attrs);
132 	mb();
133 
134 	return daddr;
135 }
136 
137 static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
138 	int nents, enum dma_data_direction direction, unsigned long attrs)
139 {
140 	int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
141 	mb();
142 	return r;
143 }
144 
145 static void octeon_dma_sync_single_for_device(struct device *dev,
146 	dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
147 {
148 	swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
149 	mb();
150 }
151 
152 static void octeon_dma_sync_sg_for_device(struct device *dev,
153 	struct scatterlist *sg, int nelems, enum dma_data_direction direction)
154 {
155 	swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
156 	mb();
157 }
158 
159 static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
160 	dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
161 {
162 	void *ret;
163 
164 	/* ignore region specifiers */
165 	gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
166 
167 	if (IS_ENABLED(CONFIG_ZONE_DMA) && dev == NULL)
168 		gfp |= __GFP_DMA;
169 	else if (IS_ENABLED(CONFIG_ZONE_DMA) &&
170 		 dev->coherent_dma_mask <= DMA_BIT_MASK(24))
171 		gfp |= __GFP_DMA;
172 	else if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
173 		 dev->coherent_dma_mask <= DMA_BIT_MASK(32))
174 		gfp |= __GFP_DMA32;
175 
176 	/* Don't invoke OOM killer */
177 	gfp |= __GFP_NORETRY;
178 
179 	ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
180 
181 	mb();
182 
183 	return ret;
184 }
185 
186 static void octeon_dma_free_coherent(struct device *dev, size_t size,
187 	void *vaddr, dma_addr_t dma_handle, unsigned long attrs)
188 {
189 	swiotlb_free_coherent(dev, size, vaddr, dma_handle);
190 }
191 
192 static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
193 {
194 	return paddr;
195 }
196 
197 static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
198 {
199 	return daddr;
200 }
201 
202 struct octeon_dma_map_ops {
203 	const struct dma_map_ops dma_map_ops;
204 	dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
205 	phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
206 };
207 
208 dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
209 {
210 	struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
211 						      struct octeon_dma_map_ops,
212 						      dma_map_ops);
213 
214 	return ops->phys_to_dma(dev, paddr);
215 }
216 EXPORT_SYMBOL(phys_to_dma);
217 
218 phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
219 {
220 	struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
221 						      struct octeon_dma_map_ops,
222 						      dma_map_ops);
223 
224 	return ops->dma_to_phys(dev, daddr);
225 }
226 EXPORT_SYMBOL(dma_to_phys);
227 
228 static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
229 	.dma_map_ops = {
230 		.alloc = octeon_dma_alloc_coherent,
231 		.free = octeon_dma_free_coherent,
232 		.map_page = octeon_dma_map_page,
233 		.unmap_page = swiotlb_unmap_page,
234 		.map_sg = octeon_dma_map_sg,
235 		.unmap_sg = swiotlb_unmap_sg_attrs,
236 		.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
237 		.sync_single_for_device = octeon_dma_sync_single_for_device,
238 		.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
239 		.sync_sg_for_device = octeon_dma_sync_sg_for_device,
240 		.mapping_error = swiotlb_dma_mapping_error,
241 		.dma_supported = swiotlb_dma_supported
242 	},
243 	.phys_to_dma = octeon_unity_phys_to_dma,
244 	.dma_to_phys = octeon_unity_dma_to_phys
245 };
246 
247 char *octeon_swiotlb;
248 
249 void __init plat_swiotlb_setup(void)
250 {
251 	int i;
252 	phys_addr_t max_addr;
253 	phys_addr_t addr_size;
254 	size_t swiotlbsize;
255 	unsigned long swiotlb_nslabs;
256 
257 	max_addr = 0;
258 	addr_size = 0;
259 
260 	for (i = 0 ; i < boot_mem_map.nr_map; i++) {
261 		struct boot_mem_map_entry *e = &boot_mem_map.map[i];
262 		if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
263 			continue;
264 
265 		/* These addresses map low for PCI. */
266 		if (e->addr > 0x410000000ull && !OCTEON_IS_OCTEON2())
267 			continue;
268 
269 		addr_size += e->size;
270 
271 		if (max_addr < e->addr + e->size)
272 			max_addr = e->addr + e->size;
273 
274 	}
275 
276 	swiotlbsize = PAGE_SIZE;
277 
278 #ifdef CONFIG_PCI
279 	/*
280 	 * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
281 	 * size to a maximum of 64MB
282 	 */
283 	if (OCTEON_IS_MODEL(OCTEON_CN31XX)
284 	    || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
285 		swiotlbsize = addr_size / 4;
286 		if (swiotlbsize > 64 * (1<<20))
287 			swiotlbsize = 64 * (1<<20);
288 	} else if (max_addr > 0xf0000000ul) {
289 		/*
290 		 * Otherwise only allocate a big iotlb if there is
291 		 * memory past the BAR1 hole.
292 		 */
293 		swiotlbsize = 64 * (1<<20);
294 	}
295 #endif
296 #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
297 	/* OCTEON II ohci is only 32-bit. */
298 	if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
299 		swiotlbsize = 64 * (1<<20);
300 #endif
301 	swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
302 	swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
303 	swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
304 
305 	octeon_swiotlb = alloc_bootmem_low_pages(swiotlbsize);
306 
307 	if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
308 		panic("Cannot allocate SWIOTLB buffer");
309 
310 	mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
311 }
312 
313 #ifdef CONFIG_PCI
314 static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
315 	.dma_map_ops = {
316 		.alloc = octeon_dma_alloc_coherent,
317 		.free = octeon_dma_free_coherent,
318 		.map_page = octeon_dma_map_page,
319 		.unmap_page = swiotlb_unmap_page,
320 		.map_sg = octeon_dma_map_sg,
321 		.unmap_sg = swiotlb_unmap_sg_attrs,
322 		.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
323 		.sync_single_for_device = octeon_dma_sync_single_for_device,
324 		.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
325 		.sync_sg_for_device = octeon_dma_sync_sg_for_device,
326 		.mapping_error = swiotlb_dma_mapping_error,
327 		.dma_supported = swiotlb_dma_supported
328 	},
329 };
330 
331 const struct dma_map_ops *octeon_pci_dma_map_ops;
332 
333 void __init octeon_pci_dma_init(void)
334 {
335 	switch (octeon_dma_bar_type) {
336 	case OCTEON_DMA_BAR_TYPE_PCIE2:
337 		_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
338 		_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
339 		break;
340 	case OCTEON_DMA_BAR_TYPE_PCIE:
341 		_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
342 		_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
343 		break;
344 	case OCTEON_DMA_BAR_TYPE_BIG:
345 		_octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
346 		_octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
347 		break;
348 	case OCTEON_DMA_BAR_TYPE_SMALL:
349 		_octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
350 		_octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
351 		break;
352 	default:
353 		BUG();
354 	}
355 	octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
356 }
357 #endif /* CONFIG_PCI */
358