1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 2 3#include "rtl83xx.dtsi" 4 5/ { 6 compatible = "realtek,rtl9302-soc"; 7 8 cpus { 9 #address-cells = <1>; 10 #size-cells = <0>; 11 12 cpu@0 { 13 device_type = "cpu"; 14 compatible = "mips,mips34Kc"; 15 reg = <0>; 16 clocks = <&baseclk 0>; 17 clock-names = "cpu"; 18 }; 19 }; 20 21 baseclk: clock-800mhz { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <800000000>; 25 }; 26 27 lx_clk: clock-175mhz { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <175000000>; 31 }; 32}; 33 34&soc { 35 intc: interrupt-controller@3000 { 36 compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; 37 reg = <0x3000 0x18>, <0x3018 0x18>; 38 interrupt-controller; 39 #interrupt-cells = <1>; 40 41 interrupt-parent = <&cpuintc>; 42 interrupts = <2>, <3>, <4>, <5>, <6>, <7>; 43 }; 44 45 spi0: spi@1200 { 46 compatible = "realtek,rtl8380-spi"; 47 reg = <0x1200 0x100>; 48 49 #address-cells = <1>; 50 #size-cells = <0>; 51 }; 52 53 timer0: timer@3200 { 54 compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; 55 reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, 56 <0x3230 0x10>, <0x3240 0x10>; 57 58 interrupt-parent = <&intc>; 59 interrupts = <7>, <8>, <9>, <10>, <11>; 60 clocks = <&lx_clk>; 61 }; 62}; 63 64&uart0 { 65 /delete-property/ clock-frequency; 66 clocks = <&lx_clk>; 67 68 interrupt-parent = <&intc>; 69 interrupts = <30>; 70}; 71 72&uart1 { 73 /delete-property/ clock-frequency; 74 clocks = <&lx_clk>; 75 76 interrupt-parent = <&intc>; 77 interrupts = <31>; 78}; 79 80