1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/mediatek,mtmips-sysc.h> 3 4/ { 5 #address-cells = <1>; 6 #size-cells = <1>; 7 compatible = "ralink,mt7628a-soc"; 8 9 cpus { 10 #address-cells = <1>; 11 #size-cells = <0>; 12 13 cpu@0 { 14 compatible = "mti,mips24KEc"; 15 device_type = "cpu"; 16 reg = <0>; 17 }; 18 }; 19 20 cpuintc: interrupt-controller { 21 #address-cells = <0>; 22 #interrupt-cells = <1>; 23 interrupt-controller; 24 compatible = "mti,cpu-interrupt-controller"; 25 }; 26 27 palmbus@10000000 { 28 compatible = "palmbus"; 29 reg = <0x10000000 0x200000>; 30 ranges = <0x0 0x10000000 0x1FFFFF>; 31 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 sysc: syscon@0 { 36 compatible = "ralink,mt7628-sysc", "ralink,mt7688-sysc", "syscon"; 37 reg = <0x0 0x60>; 38 #clock-cells = <1>; 39 #reset-cells = <1>; 40 }; 41 42 pinmux: pinmux@60 { 43 compatible = "pinctrl-single"; 44 reg = <0x60 0x8>; 45 #address-cells = <1>; 46 #size-cells = <0>; 47 #pinctrl-cells = <2>; 48 pinctrl-single,bit-per-mux; 49 pinctrl-single,register-width = <32>; 50 pinctrl-single,function-mask = <0x1>; 51 52 pinmux_gpio_gpio: gpio-gpio-pins { 53 pinctrl-single,bits = <0x0 0x0 0x3>; 54 }; 55 56 pinmux_spi_cs1_cs: spi-cs1-cs-pins { 57 pinctrl-single,bits = <0x0 0x0 0x30>; 58 }; 59 60 pinmux_i2s_gpio: i2s-gpio-pins { 61 pinctrl-single,bits = <0x0 0x40 0xc0>; 62 }; 63 64 pinmux_uart0_uart: uart0-uart0-pins { 65 pinctrl-single,bits = <0x0 0x0 0x300>; 66 }; 67 68 pinmux_sdmode_sdxc: sdmode-sdxc-pins { 69 pinctrl-single,bits = <0x0 0x0 0xc00>; 70 }; 71 72 pinmux_sdmode_gpio: sdmode-gpio-pins { 73 pinctrl-single,bits = <0x0 0x400 0xc00>; 74 }; 75 76 pinmux_spi_spi: spi-spi-pins { 77 pinctrl-single,bits = <0x0 0x0 0x1000>; 78 }; 79 80 pinmux_refclk_gpio: refclk-gpio-pins { 81 pinctrl-single,bits = <0x0 0x40000 0x40000>; 82 }; 83 84 pinmux_i2c_i2c: i2c-i2c-pins { 85 pinctrl-single,bits = <0x0 0x0 0x300000>; 86 }; 87 88 pinmux_uart1_uart: uart1-uart1-pins { 89 pinctrl-single,bits = <0x0 0x0 0x3000000>; 90 }; 91 92 pinmux_uart2_uart: uart2-uart-pins { 93 pinctrl-single,bits = <0x0 0x0 0xc000000>; 94 }; 95 96 pinmux_pwm0_pwm: pwm0-pwm-pins { 97 pinctrl-single,bits = <0x0 0x0 0x30000000>; 98 }; 99 100 pinmux_pwm0_gpio: pwm0-gpio-pins { 101 pinctrl-single,bits = <0x0 0x10000000 102 0x30000000>; 103 }; 104 105 pinmux_pwm1_pwm: pwm1-pwm-pins { 106 pinctrl-single,bits = <0x0 0x0 0xc0000000>; 107 }; 108 109 pinmux_pwm1_gpio: pwm1-gpio-pins { 110 pinctrl-single,bits = <0x0 0x40000000 111 0xc0000000>; 112 }; 113 114 pinmux_p0led_an_gpio: p0led-an-gpio-pins { 115 pinctrl-single,bits = <0x4 0x4 0xc>; 116 }; 117 118 pinmux_p1led_an_gpio: p1led-an-gpio-pins { 119 pinctrl-single,bits = <0x4 0x10 0x30>; 120 }; 121 122 pinmux_p2led_an_gpio: p2led-an-gpio-pins { 123 pinctrl-single,bits = <0x4 0x40 0xc0>; 124 }; 125 126 pinmux_p3led_an_gpio: p3led-an-gpio-pins { 127 pinctrl-single,bits = <0x4 0x100 0x300>; 128 }; 129 130 pinmux_p4led_an_gpio: p4led-an-gpio-pins { 131 pinctrl-single,bits = <0x4 0x400 0xc00>; 132 }; 133 }; 134 135 watchdog: watchdog@100 { 136 compatible = "mediatek,mt7621-wdt"; 137 reg = <0x100 0x100>; 138 mediatek,sysctl = <&sysc>; 139 140 status = "disabled"; 141 }; 142 143 intc: interrupt-controller@200 { 144 compatible = "ralink,rt2880-intc"; 145 reg = <0x200 0x100>; 146 147 interrupt-controller; 148 #interrupt-cells = <1>; 149 150 resets = <&sysc 9>; 151 reset-names = "intc"; 152 153 interrupt-parent = <&cpuintc>; 154 interrupts = <2>; 155 156 ralink,intc-registers = <0x9c 0xa0 157 0x6c 0xa4 158 0x80 0x78>; 159 }; 160 161 memory-controller@300 { 162 compatible = "ralink,mt7620a-memc"; 163 reg = <0x300 0x100>; 164 }; 165 166 gpio: gpio@600 { 167 compatible = "mediatek,mt7621-gpio"; 168 reg = <0x600 0x100>; 169 170 gpio-controller; 171 interrupt-controller; 172 #gpio-cells = <2>; 173 #interrupt-cells = <2>; 174 175 interrupt-parent = <&intc>; 176 interrupts = <6>; 177 }; 178 179 spi: spi@b00 { 180 compatible = "ralink,mt7621-spi"; 181 reg = <0xb00 0x100>; 182 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinmux_spi_spi>; 185 186 clocks = <&sysc MT76X8_CLK_SPI1>; 187 188 resets = <&sysc 18>; 189 reset-names = "spi"; 190 191 #address-cells = <1>; 192 #size-cells = <0>; 193 194 status = "disabled"; 195 }; 196 197 i2c: i2c@900 { 198 compatible = "mediatek,mt7621-i2c"; 199 reg = <0x900 0x100>; 200 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinmux_i2c_i2c>; 203 204 clocks = <&sysc MT76X8_CLK_I2C>; 205 206 resets = <&sysc 16>; 207 reset-names = "i2c"; 208 209 #address-cells = <1>; 210 #size-cells = <0>; 211 212 status = "disabled"; 213 }; 214 215 uart0: uartlite@c00 { 216 compatible = "ns16550a"; 217 reg = <0xc00 0x100>; 218 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinmux_uart0_uart>; 221 222 clocks = <&sysc MT76X8_CLK_UART0>; 223 224 resets = <&sysc 12>; 225 reset-names = "uart0"; 226 227 interrupt-parent = <&intc>; 228 interrupts = <20>; 229 230 reg-shift = <2>; 231 }; 232 233 uart1: uart1@d00 { 234 compatible = "ns16550a"; 235 reg = <0xd00 0x100>; 236 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinmux_uart1_uart>; 239 240 clocks = <&sysc MT76X8_CLK_UART1>; 241 242 resets = <&sysc 19>; 243 reset-names = "uart1"; 244 245 interrupt-parent = <&intc>; 246 interrupts = <21>; 247 248 reg-shift = <2>; 249 }; 250 251 uart2: uart2@e00 { 252 compatible = "ns16550a"; 253 reg = <0xe00 0x100>; 254 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinmux_uart2_uart>; 257 258 clocks = <&sysc MT76X8_CLK_UART2>; 259 260 resets = <&sysc 20>; 261 reset-names = "uart2"; 262 263 interrupt-parent = <&intc>; 264 interrupts = <22>; 265 266 reg-shift = <2>; 267 }; 268 }; 269 270 usb_phy: usb-phy@10120000 { 271 compatible = "mediatek,mt7628-usbphy"; 272 reg = <0x10120000 0x1000>; 273 274 #phy-cells = <0>; 275 276 ralink,sysctl = <&sysc>; 277 resets = <&sysc 22 &sysc 25>; 278 reset-names = "host", "device"; 279 }; 280 281 usb@101c0000 { 282 compatible = "generic-ehci"; 283 reg = <0x101c0000 0x1000>; 284 285 phys = <&usb_phy>; 286 phy-names = "usb"; 287 288 interrupt-parent = <&intc>; 289 interrupts = <18>; 290 }; 291 292 wmac: wmac@10300000 { 293 compatible = "mediatek,mt7628-wmac"; 294 reg = <0x10300000 0x100000>; 295 296 clocks = <&sysc MT76X8_CLK_WMAC>; 297 298 interrupt-parent = <&cpuintc>; 299 interrupts = <6>; 300 301 status = "disabled"; 302 }; 303}; 304