1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2#include <dt-bindings/interrupt-controller/mips-gic.h> 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/clock/mt7621-clk.h> 5#include <dt-bindings/reset/mt7621-reset.h> 6 7/ { 8 #address-cells = <1>; 9 #size-cells = <1>; 10 compatible = "mediatek,mt7621-soc"; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "mips,mips1004Kc"; 19 reg = <0>; 20 }; 21 22 cpu@1 { 23 device_type = "cpu"; 24 compatible = "mips,mips1004Kc"; 25 reg = <1>; 26 }; 27 }; 28 29 cpuintc: cpuintc { 30 #address-cells = <0>; 31 #interrupt-cells = <1>; 32 interrupt-controller; 33 compatible = "mti,cpu-interrupt-controller"; 34 }; 35 36 mmc_fixed_3v3: regulator-3v3 { 37 compatible = "regulator-fixed"; 38 regulator-name = "mmc_power"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 enable-active-high; 42 regulator-always-on; 43 }; 44 45 mmc_fixed_1v8_io: regulator-1v8 { 46 compatible = "regulator-fixed"; 47 regulator-name = "mmc_io"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 enable-active-high; 51 regulator-always-on; 52 }; 53 54 palmbus: palmbus@1e000000 { 55 compatible = "palmbus"; 56 reg = <0x1e000000 0x100000>; 57 ranges = <0x0 0x1e000000 0x0fffff>; 58 59 #address-cells = <1>; 60 #size-cells = <1>; 61 62 sysc: syscon@0 { 63 compatible = "mediatek,mt7621-sysc", "syscon"; 64 reg = <0x0 0x100>; 65 #clock-cells = <1>; 66 #reset-cells = <1>; 67 ralink,memctl = <&memc>; 68 clock-output-names = "xtal", "cpu", "bus", 69 "50m", "125m", "150m", 70 "250m", "270m"; 71 }; 72 73 wdt: watchdog@100 { 74 compatible = "mediatek,mt7621-wdt"; 75 reg = <0x100 0x100>; 76 mediatek,sysctl = <&sysc>; 77 }; 78 79 gpio: gpio@600 { 80 #gpio-cells = <2>; 81 #interrupt-cells = <2>; 82 compatible = "mediatek,mt7621-gpio"; 83 gpio-controller; 84 gpio-ranges = <&pinctrl 0 0 95>; 85 interrupt-controller; 86 reg = <0x600 0x100>; 87 interrupt-parent = <&gic>; 88 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 89 }; 90 91 i2c: i2c@900 { 92 compatible = "mediatek,mt7621-i2c"; 93 reg = <0x900 0x100>; 94 95 clocks = <&sysc MT7621_CLK_I2C>; 96 clock-names = "i2c"; 97 resets = <&sysc MT7621_RST_I2C>; 98 reset-names = "i2c"; 99 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 status = "disabled"; 104 105 pinctrl-names = "default"; 106 pinctrl-0 = <&i2c_pins>; 107 }; 108 109 memc: memory-controller@5000 { 110 compatible = "mediatek,mt7621-memc", "syscon"; 111 reg = <0x5000 0x1000>; 112 }; 113 114 serial0: serial@c00 { 115 compatible = "ns16550a"; 116 reg = <0xc00 0x100>; 117 118 reg-io-width = <4>; 119 reg-shift = <2>; 120 121 clocks = <&sysc MT7621_CLK_UART1>; 122 123 interrupt-parent = <&gic>; 124 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; 125 126 no-loopback-test; 127 128 pinctrl-names = "default"; 129 pinctrl-0 = <&uart1_pins>; 130 }; 131 132 serial1: serial@d00 { 133 compatible = "ns16550a"; 134 reg = <0xd00 0x100>; 135 136 reg-io-width = <4>; 137 reg-shift = <2>; 138 139 clocks = <&sysc MT7621_CLK_UART2>; 140 141 interrupt-parent = <&gic>; 142 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>; 143 144 no-loopback-test; 145 146 pinctrl-names = "default"; 147 pinctrl-0 = <&uart2_pins>; 148 149 status = "disabled"; 150 }; 151 152 serial2: serial@e00 { 153 compatible = "ns16550a"; 154 reg = <0xe00 0x100>; 155 156 reg-io-width = <4>; 157 reg-shift = <2>; 158 159 clocks = <&sysc MT7621_CLK_UART3>; 160 161 interrupt-parent = <&gic>; 162 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>; 163 164 no-loopback-test; 165 166 pinctrl-names = "default"; 167 pinctrl-0 = <&uart3_pins>; 168 169 status = "disabled"; 170 }; 171 172 spi0: spi@b00 { 173 status = "disabled"; 174 175 compatible = "ralink,mt7621-spi"; 176 reg = <0xb00 0x100>; 177 178 clocks = <&sysc MT7621_CLK_SPI>; 179 clock-names = "spi"; 180 181 resets = <&sysc MT7621_RST_SPI>; 182 reset-names = "spi"; 183 184 #address-cells = <1>; 185 #size-cells = <0>; 186 187 pinctrl-names = "default"; 188 pinctrl-0 = <&spi_pins>; 189 }; 190 }; 191 192 pinctrl: pinctrl { 193 compatible = "ralink,mt7621-pinctrl"; 194 195 i2c_pins: i2c0-pins { 196 pinmux { 197 groups = "i2c"; 198 function = "i2c"; 199 }; 200 }; 201 202 spi_pins: spi0-pins { 203 pinmux { 204 groups = "spi"; 205 function = "spi"; 206 }; 207 }; 208 209 uart1_pins: uart1-pins { 210 pinmux { 211 groups = "uart1"; 212 function = "uart1"; 213 }; 214 }; 215 216 uart2_pins: uart2-pins { 217 pinmux { 218 groups = "uart2"; 219 function = "uart2"; 220 }; 221 }; 222 223 uart3_pins: uart3-pins { 224 pinmux { 225 groups = "uart3"; 226 function = "uart3"; 227 }; 228 }; 229 230 rgmii1_pins: rgmii1-pins { 231 pinmux { 232 groups = "rgmii1"; 233 function = "rgmii1"; 234 }; 235 }; 236 237 rgmii2_pins: rgmii2-pins { 238 pinmux { 239 groups = "rgmii2"; 240 function = "rgmii2"; 241 }; 242 }; 243 244 mdio_pins: mdio0-pins { 245 pinmux { 246 groups = "mdio"; 247 function = "mdio"; 248 }; 249 }; 250 251 pcie_pins: pcie0-pins { 252 pinmux { 253 groups = "pcie"; 254 function = "gpio"; 255 }; 256 }; 257 258 nand_pins: nand0-pins { 259 spi-pinmux { 260 groups = "spi"; 261 function = "nand1"; 262 }; 263 264 sdhci-pinmux { 265 groups = "sdhci"; 266 function = "nand2"; 267 }; 268 }; 269 270 sdhci_pins: sdhci0-pins { 271 pinmux { 272 groups = "sdhci"; 273 function = "sdhci"; 274 }; 275 }; 276 }; 277 278 mmc: mmc@1e130000 { 279 status = "disabled"; 280 281 compatible = "mediatek,mt7620-mmc"; 282 reg = <0x1e130000 0x4000>; 283 284 bus-width = <4>; 285 max-frequency = <48000000>; 286 cap-sd-highspeed; 287 cap-mmc-highspeed; 288 vmmc-supply = <&mmc_fixed_3v3>; 289 vqmmc-supply = <&mmc_fixed_1v8_io>; 290 disable-wp; 291 292 pinctrl-names = "default", "state_uhs"; 293 pinctrl-0 = <&sdhci_pins>; 294 pinctrl-1 = <&sdhci_pins>; 295 296 clocks = <&sysc MT7621_CLK_SHXC>, 297 <&sysc MT7621_CLK_50M>; 298 clock-names = "source", "hclk"; 299 300 interrupt-parent = <&gic>; 301 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; 302 }; 303 304 usb: usb@1e1c0000 { 305 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci"; 306 reg = <0x1e1c0000 0x1000 307 0x1e1d0700 0x0100>; 308 reg-names = "mac", "ippc"; 309 310 #address-cells = <1>; 311 #size-cells = <0>; 312 313 clocks = <&sysc MT7621_CLK_XTAL>; 314 clock-names = "sys_ck"; 315 316 interrupt-parent = <&gic>; 317 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; 318 }; 319 320 gic: interrupt-controller@1fbc0000 { 321 compatible = "mti,gic"; 322 reg = <0x1fbc0000 0x2000>; 323 324 interrupt-controller; 325 #interrupt-cells = <3>; 326 327 mti,reserved-cpu-vectors = <7>; 328 329 timer { 330 compatible = "mti,gic-timer"; 331 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 332 clocks = <&sysc MT7621_CLK_CPU>; 333 }; 334 }; 335 336 cpc: cpc@1fbf0000 { 337 compatible = "mti,mips-cpc"; 338 reg = <0x1fbf0000 0x8000>; 339 }; 340 341 cdmm: cdmm@1fbf8000 { 342 compatible = "mti,mips-cdmm"; 343 reg = <0x1fbf8000 0x8000>; 344 }; 345 346 ethernet: ethernet@1e100000 { 347 compatible = "mediatek,mt7621-eth"; 348 reg = <0x1e100000 0x10000>; 349 350 clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; 351 clock-names = "fe", "ethif"; 352 353 #address-cells = <1>; 354 #size-cells = <0>; 355 356 resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; 357 reset-names = "fe", "eth"; 358 359 interrupt-parent = <&gic>; 360 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; 361 362 mediatek,ethsys = <&sysc>; 363 364 pinctrl-names = "default"; 365 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; 366 367 gmac0: mac@0 { 368 compatible = "mediatek,eth-mac"; 369 reg = <0>; 370 phy-mode = "trgmii"; 371 372 fixed-link { 373 speed = <1000>; 374 full-duplex; 375 pause; 376 }; 377 }; 378 379 gmac1: mac@1 { 380 compatible = "mediatek,eth-mac"; 381 reg = <1>; 382 phy-mode = "rgmii"; 383 384 fixed-link { 385 speed = <1000>; 386 full-duplex; 387 pause; 388 }; 389 }; 390 391 mdio: mdio-bus { 392 #address-cells = <1>; 393 #size-cells = <0>; 394 395 switch0: switch@1f { 396 compatible = "mediatek,mt7621"; 397 reg = <0x1f>; 398 mediatek,mcm; 399 resets = <&sysc MT7621_RST_MCM>; 400 reset-names = "mcm"; 401 interrupt-controller; 402 #interrupt-cells = <1>; 403 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 404 405 ports { 406 #address-cells = <1>; 407 #size-cells = <0>; 408 409 port@0 { 410 status = "disabled"; 411 reg = <0>; 412 label = "swp0"; 413 }; 414 415 port@1 { 416 status = "disabled"; 417 reg = <1>; 418 label = "swp1"; 419 }; 420 421 port@2 { 422 status = "disabled"; 423 reg = <2>; 424 label = "swp2"; 425 }; 426 427 port@3 { 428 status = "disabled"; 429 reg = <3>; 430 label = "swp3"; 431 }; 432 433 port@4 { 434 status = "disabled"; 435 reg = <4>; 436 label = "swp4"; 437 }; 438 439 port@5 { 440 reg = <5>; 441 ethernet = <&gmac1>; 442 phy-mode = "rgmii"; 443 444 fixed-link { 445 speed = <1000>; 446 full-duplex; 447 pause; 448 }; 449 }; 450 451 port@6 { 452 reg = <6>; 453 ethernet = <&gmac0>; 454 phy-mode = "trgmii"; 455 456 fixed-link { 457 speed = <1000>; 458 full-duplex; 459 pause; 460 }; 461 }; 462 }; 463 }; 464 }; 465 }; 466 467 pcie: pcie@1e140000 { 468 compatible = "mediatek,mt7621-pci"; 469 reg = <0x1e140000 0x100>, /* host-pci bridge registers */ 470 <0x1e142000 0x100>, /* pcie port 0 RC control registers */ 471 <0x1e143000 0x100>, /* pcie port 1 RC control registers */ 472 <0x1e144000 0x100>; /* pcie port 2 RC control registers */ 473 #address-cells = <3>; 474 #size-cells = <2>; 475 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pcie_pins>; 478 479 device_type = "pci"; 480 481 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ 482 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ 483 484 #interrupt-cells = <1>; 485 interrupt-map-mask = <0xF800 0 0 0>; 486 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, 487 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 488 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 489 490 status = "disabled"; 491 492 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; 493 494 pcie@0,0 { 495 reg = <0x0000 0 0 0 0>; 496 #address-cells = <3>; 497 #size-cells = <2>; 498 device_type = "pci"; 499 #interrupt-cells = <1>; 500 interrupt-map-mask = <0 0 0 0>; 501 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; 502 resets = <&sysc MT7621_RST_PCIE0>; 503 clocks = <&sysc MT7621_CLK_PCIE0>; 504 phys = <&pcie0_phy 1>; 505 phy-names = "pcie-phy0"; 506 ranges; 507 }; 508 509 pcie@1,0 { 510 reg = <0x0800 0 0 0 0>; 511 #address-cells = <3>; 512 #size-cells = <2>; 513 device_type = "pci"; 514 #interrupt-cells = <1>; 515 interrupt-map-mask = <0 0 0 0>; 516 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; 517 resets = <&sysc MT7621_RST_PCIE1>; 518 clocks = <&sysc MT7621_CLK_PCIE1>; 519 phys = <&pcie0_phy 1>; 520 phy-names = "pcie-phy1"; 521 ranges; 522 }; 523 524 pcie@2,0 { 525 reg = <0x1000 0 0 0 0>; 526 #address-cells = <3>; 527 #size-cells = <2>; 528 device_type = "pci"; 529 #interrupt-cells = <1>; 530 interrupt-map-mask = <0 0 0 0>; 531 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 532 resets = <&sysc MT7621_RST_PCIE2>; 533 clocks = <&sysc MT7621_CLK_PCIE2>; 534 phys = <&pcie2_phy 0>; 535 phy-names = "pcie-phy2"; 536 ranges; 537 }; 538 }; 539 540 pcie0_phy: pcie-phy@1e149000 { 541 compatible = "mediatek,mt7621-pci-phy"; 542 reg = <0x1e149000 0x0700>; 543 clocks = <&sysc MT7621_CLK_XTAL>; 544 #phy-cells = <1>; 545 }; 546 547 pcie2_phy: pcie-phy@1e14a000 { 548 compatible = "mediatek,mt7621-pci-phy"; 549 reg = <0x1e14a000 0x0700>; 550 clocks = <&sysc MT7621_CLK_XTAL>; 551 #phy-cells = <1>; 552 }; 553}; 554