xref: /linux/arch/mips/boot/dts/mscc/ocelot.dtsi (revision b7d3826c2ed6c3e626e7ae796c5df2c0d2551c6a) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/ {
5	#address-cells = <1>;
6	#size-cells = <1>;
7	compatible = "mscc,ocelot";
8
9	cpus {
10		#address-cells = <1>;
11		#size-cells = <0>;
12
13		cpu@0 {
14			compatible = "mips,mips24KEc";
15			device_type = "cpu";
16			clocks = <&cpu_clk>;
17			reg = <0>;
18		};
19	};
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	cpuintc: interrupt-controller {
26		#address-cells = <0>;
27		#interrupt-cells = <1>;
28		interrupt-controller;
29		compatible = "mti,cpu-interrupt-controller";
30	};
31
32	cpu_clk: cpu-clock {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <500000000>;
36	};
37
38	ahb_clk: ahb-clk {
39		compatible = "fixed-factor-clock";
40		#clock-cells = <0>;
41		clocks = <&cpu_clk>;
42		clock-div = <2>;
43		clock-mult = <1>;
44	};
45
46	ahb@70000000 {
47		compatible = "simple-bus";
48		#address-cells = <1>;
49		#size-cells = <1>;
50		ranges = <0 0x70000000 0x2000000>;
51
52		interrupt-parent = <&intc>;
53
54		cpu_ctrl: syscon@0 {
55			compatible = "mscc,ocelot-cpu-syscon", "syscon";
56			reg = <0x0 0x2c>;
57		};
58
59		intc: interrupt-controller@70 {
60			compatible = "mscc,ocelot-icpu-intr";
61			reg = <0x70 0x70>;
62			#interrupt-cells = <1>;
63			interrupt-controller;
64			interrupt-parent = <&cpuintc>;
65			interrupts = <2>;
66		};
67
68		uart0: serial@100000 {
69			pinctrl-0 = <&uart_pins>;
70			pinctrl-names = "default";
71			compatible = "ns16550a";
72			reg = <0x100000 0x20>;
73			interrupts = <6>;
74			clocks = <&ahb_clk>;
75			reg-io-width = <4>;
76			reg-shift = <2>;
77
78			status = "disabled";
79		};
80
81		uart2: serial@100800 {
82			pinctrl-0 = <&uart2_pins>;
83			pinctrl-names = "default";
84			compatible = "ns16550a";
85			reg = <0x100800 0x20>;
86			interrupts = <7>;
87			clocks = <&ahb_clk>;
88			reg-io-width = <4>;
89			reg-shift = <2>;
90
91			status = "disabled";
92		};
93
94		spi: spi@101000 {
95			compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
96			#address-cells = <1>;
97			#size-cells = <0>;
98			reg = <0x101000 0x100>, <0x3c 0x18>;
99			interrupts = <9>;
100			clocks = <&ahb_clk>;
101
102			status = "disabled";
103		};
104
105		switch@1010000 {
106			compatible = "mscc,vsc7514-switch";
107			reg = <0x1010000 0x10000>,
108			      <0x1030000 0x10000>,
109			      <0x1080000 0x100>,
110			      <0x11e0000 0x100>,
111			      <0x11f0000 0x100>,
112			      <0x1200000 0x100>,
113			      <0x1210000 0x100>,
114			      <0x1220000 0x100>,
115			      <0x1230000 0x100>,
116			      <0x1240000 0x100>,
117			      <0x1250000 0x100>,
118			      <0x1260000 0x100>,
119			      <0x1270000 0x100>,
120			      <0x1280000 0x100>,
121			      <0x1800000 0x80000>,
122			      <0x1880000 0x10000>;
123			reg-names = "sys", "rew", "qs", "port0", "port1",
124				    "port2", "port3", "port4", "port5", "port6",
125				    "port7", "port8", "port9", "port10", "qsys",
126				    "ana";
127			interrupts = <21 22>;
128			interrupt-names = "xtr", "inj";
129
130			ethernet-ports {
131				#address-cells = <1>;
132				#size-cells = <0>;
133
134				port0: port@0 {
135					reg = <0>;
136				};
137				port1: port@1 {
138					reg = <1>;
139				};
140				port2: port@2 {
141					reg = <2>;
142				};
143				port3: port@3 {
144					reg = <3>;
145				};
146				port4: port@4 {
147					reg = <4>;
148				};
149				port5: port@5 {
150					reg = <5>;
151				};
152				port6: port@6 {
153					reg = <6>;
154				};
155				port7: port@7 {
156					reg = <7>;
157				};
158				port8: port@8 {
159					reg = <8>;
160				};
161				port9: port@9 {
162					reg = <9>;
163				};
164				port10: port@10 {
165					reg = <10>;
166				};
167			};
168		};
169
170		reset@1070008 {
171			compatible = "mscc,ocelot-chip-reset";
172			reg = <0x1070008 0x4>;
173		};
174
175		gpio: pinctrl@1070034 {
176			compatible = "mscc,ocelot-pinctrl";
177			reg = <0x1070034 0x68>;
178			gpio-controller;
179			#gpio-cells = <2>;
180			gpio-ranges = <&gpio 0 0 22>;
181			interrupt-controller;
182			interrupts = <13>;
183			#interrupt-cells = <2>;
184
185			uart_pins: uart-pins {
186				pins = "GPIO_6", "GPIO_7";
187				function = "uart";
188			};
189
190			uart2_pins: uart2-pins {
191				pins = "GPIO_12", "GPIO_13";
192				function = "uart2";
193			};
194
195			miim1: miim1 {
196				pins = "GPIO_14", "GPIO_15";
197				function = "miim1";
198			};
199		};
200
201		mdio0: mdio@107009c {
202			#address-cells = <1>;
203			#size-cells = <0>;
204			compatible = "mscc,ocelot-miim";
205			reg = <0x107009c 0x24>, <0x10700f0 0x8>;
206			interrupts = <14>;
207			status = "disabled";
208
209			phy0: ethernet-phy@0 {
210				reg = <0>;
211			};
212			phy1: ethernet-phy@1 {
213				reg = <1>;
214			};
215			phy2: ethernet-phy@2 {
216				reg = <2>;
217			};
218			phy3: ethernet-phy@3 {
219				reg = <3>;
220			};
221		};
222
223		mdio1: mdio@10700c0 {
224			#address-cells = <1>;
225			#size-cells = <0>;
226			compatible = "mscc,ocelot-miim";
227			reg = <0x10700c0 0x24>;
228			interrupts = <15>;
229			pinctrl-names = "default";
230			pinctrl-0 = <&miim1>;
231			status = "disabled";
232		};
233
234		hsio: syscon@10d0000 {
235			compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
236			reg = <0x10d0000 0x10000>;
237
238			serdes: serdes {
239				compatible = "mscc,vsc7514-serdes";
240				#phy-cells = <2>;
241			};
242		};
243	};
244};
245