1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2/* 3 * Copyright 2024 Mobileye Vision Technologies Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/mips-gic.h> 7 8#include <dt-bindings/clock/mobileye,eyeq5-clk.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "img,i6500"; 19 reg = <0>; 20 clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>; 21 }; 22 }; 23 24 aliases { 25 serial0 = &uart0; 26 }; 27 28 cpu_intc: interrupt-controller { 29 compatible = "mti,cpu-interrupt-controller"; 30 interrupt-controller; 31 #address-cells = <0>; 32 #interrupt-cells = <1>; 33 }; 34 35 xtal: clock-30000000 { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <30000000>; 39 }; 40 41 soc: soc { 42 compatible = "simple-bus"; 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 olb_acc: system-controller@d2003000 { 48 compatible = "mobileye,eyeq6h-acc-olb", "syscon"; 49 reg = <0x0 0xd2003000 0x0 0x1000>; 50 #reset-cells = <1>; 51 #clock-cells = <1>; 52 clocks = <&xtal>; 53 clock-names = "ref"; 54 }; 55 56 olb_central: system-controller@d3100000 { 57 compatible = "mobileye,eyeq6h-central-olb", "syscon"; 58 reg = <0x0 0xd3100000 0x0 0x1000>; 59 #clock-cells = <1>; 60 clocks = <&xtal>; 61 clock-names = "ref"; 62 }; 63 64 uart0: serial@d3331000 { 65 compatible = "arm,pl011", "arm,primecell"; 66 reg = <0 0xd3331000 0x0 0x1000>; 67 reg-io-width = <4>; 68 interrupt-parent = <&gic>; 69 interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>; 70 clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>; 71 clock-names = "uartclk", "apb_pclk"; 72 }; 73 74 pinctrl_west: pinctrl@d3337000 { 75 compatible = "pinctrl-single"; 76 reg = <0x0 0xd3337000 0x0 0xb0>; 77 #pinctrl-cells = <1>; 78 pinctrl-single,register-width = <32>; 79 pinctrl-single,function-mask = <0xffff>; 80 }; 81 82 olb_west: system-controller@d3338000 { 83 compatible = "mobileye,eyeq6h-west-olb", "syscon"; 84 reg = <0x0 0xd3338000 0x0 0x1000>; 85 #reset-cells = <1>; 86 #clock-cells = <1>; 87 clocks = <&xtal>; 88 clock-names = "ref"; 89 }; 90 91 pinctrl_east: pinctrl@d3357000 { 92 compatible = "pinctrl-single"; 93 reg = <0x0 0xd3357000 0x0 0xb0>; 94 #pinctrl-cells = <1>; 95 pinctrl-single,register-width = <32>; 96 pinctrl-single,function-mask = <0xffff>; 97 }; 98 99 olb_east: system-controller@d3358000 { 100 compatible = "mobileye,eyeq6h-east-olb", "syscon"; 101 reg = <0x0 0xd3358000 0x0 0x1000>; 102 #reset-cells = <1>; 103 #clock-cells = <1>; 104 clocks = <&xtal>; 105 clock-names = "ref"; 106 }; 107 108 olb_south: system-controller@d8013000 { 109 compatible = "mobileye,eyeq6h-south-olb", "syscon"; 110 reg = <0x0 0xd8013000 0x0 0x1000>; 111 #clock-cells = <1>; 112 clocks = <&xtal>; 113 clock-names = "ref"; 114 }; 115 116 pinctrl_south: pinctrl@d8014000 { 117 compatible = "pinctrl-single"; 118 reg = <0x0 0xd8014000 0x0 0xf8>; 119 #pinctrl-cells = <1>; 120 pinctrl-single,register-width = <32>; 121 pinctrl-single,function-mask = <0xffff>; 122 }; 123 124 olb_ddr0: system-controller@e4080000 { 125 compatible = "mobileye,eyeq6h-ddr0-olb", "syscon"; 126 reg = <0x0 0xe4080000 0x0 0x1000>; 127 #clock-cells = <1>; 128 clocks = <&xtal>; 129 clock-names = "ref"; 130 }; 131 132 olb_ddr1: system-controller@e4081000 { 133 compatible = "mobileye,eyeq6h-ddr1-olb", "syscon"; 134 reg = <0x0 0xe4081000 0x0 0x1000>; 135 #clock-cells = <1>; 136 clocks = <&xtal>; 137 clock-names = "ref"; 138 }; 139 140 gic: interrupt-controller@f0920000 { 141 compatible = "mti,gic"; 142 reg = <0x0 0xf0920000 0x0 0x20000>; 143 interrupt-controller; 144 #interrupt-cells = <3>; 145 146 /* 147 * Declare the interrupt-parent even though the mti,gic 148 * binding doesn't require it, such that the kernel can 149 * figure out that cpu_intc is the root interrupt 150 * controller & should be probed first. 151 */ 152 interrupt-parent = <&cpu_intc>; 153 154 timer { 155 compatible = "mti,gic-timer"; 156 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 157 clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>; 158 }; 159 }; 160 }; 161}; 162 163#include "eyeq6h-pins.dtsi" 164