1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2/* 3* Copyright 2023 Mobileye Vision Technologies Ltd. 4*/ 5 6#include <dt-bindings/interrupt-controller/mips-gic.h> 7 8#include <dt-bindings/clock/mobileye,eyeq5-clk.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "img,i6500"; 19 reg = <0>; 20 clocks = <&olb EQ5C_CPU_CORE0>; 21 }; 22 }; 23 24 reserved-memory { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 29 /* These reserved memory regions are also defined in bootmanager 30 * for configuring inbound translation for BARS, don't change 31 * these without syncing with bootmanager 32 */ 33 shmem0_reserved: shmem@804000000 { 34 reg = <0x8 0x04000000 0x0 0x1000000>; 35 }; 36 shmem1_reserved: shmem@805000000 { 37 reg = <0x8 0x05000000 0x0 0x1000000>; 38 }; 39 pci0_msi_reserved: pci0-msi@806000000 { 40 reg = <0x8 0x06000000 0x0 0x100000>; 41 }; 42 pci1_msi_reserved: pci1-msi@806100000 { 43 reg = <0x8 0x06100000 0x0 0x100000>; 44 }; 45 46 mini_coredump0_reserved: mini-coredump0@806200000 { 47 reg = <0x8 0x06200000 0x0 0x100000>; 48 }; 49 mhm_reserved_0: the-mhm-reserved-0@0 { 50 reg = <0x8 0x00000000 0x0 0x0000800>; 51 }; 52 53 nvram@461fe00 { 54 compatible = "mobileye,eyeq5-bootloader-config", "nvmem-rmem"; 55 reg = <0x0 0x0461fe00 0x0 0x200>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 no-map; 59 60 nvmem-layout { 61 compatible = "fixed-layout"; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 65 eth0_mac: mac@7c { 66 reg = <0x7c 0x6>; 67 }; 68 69 eth1_mac: mac@82 { 70 reg = <0x82 0x6>; 71 }; 72 }; 73 }; 74 }; 75 76 aliases { 77 serial0 = &uart0; 78 serial1 = &uart1; 79 serial2 = &uart2; 80 ethernet0 = &macb0; 81 ethernet1 = &macb1; 82 }; 83 84 cpu_intc: interrupt-controller { 85 compatible = "mti,cpu-interrupt-controller"; 86 interrupt-controller; 87 #address-cells = <0>; 88 #interrupt-cells = <1>; 89 }; 90 91 xtal: xtal { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <30000000>; 95 }; 96 97 pclk: pclk { 98 compatible = "fixed-clock"; 99 #clock-cells = <0>; 100 clock-frequency = <250000000>; /* 250MHz */ 101 }; 102 103 tsu_clk: tsu-clk { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <125000000>; /* 125MHz */ 107 }; 108 109 soc: soc { 110 #address-cells = <2>; 111 #size-cells = <2>; 112 ranges; 113 compatible = "simple-bus"; 114 115 i2c0: i2c@300000 { 116 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 117 reg = <0 0x300000 0x0 0x1000>; 118 interrupt-parent = <&gic>; 119 interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; 120 clock-frequency = <400000>; /* Fast mode */ 121 #address-cells = <1>; 122 #size-cells = <0>; 123 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 124 clock-names = "i2cclk", "apb_pclk"; 125 resets = <&olb 0 13>; 126 i2c-transfer-timeout-us = <10000>; 127 mobileye,olb = <&olb 0>; 128 }; 129 130 i2c1: i2c@400000 { 131 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 132 reg = <0 0x400000 0x0 0x1000>; 133 interrupt-parent = <&gic>; 134 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; 135 clock-frequency = <400000>; /* Fast mode */ 136 #address-cells = <1>; 137 #size-cells = <0>; 138 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 139 clock-names = "i2cclk", "apb_pclk"; 140 resets = <&olb 0 14>; 141 i2c-transfer-timeout-us = <10000>; 142 mobileye,olb = <&olb 1>; 143 }; 144 145 i2c2: i2c@500000 { 146 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 147 reg = <0 0x500000 0x0 0x1000>; 148 interrupt-parent = <&gic>; 149 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; 150 clock-frequency = <400000>; /* Fast mode */ 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 154 clock-names = "i2cclk", "apb_pclk"; 155 resets = <&olb 0 15>; 156 i2c-transfer-timeout-us = <10000>; 157 mobileye,olb = <&olb 2>; 158 }; 159 160 i2c3: i2c@600000 { 161 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 162 reg = <0 0x600000 0x0 0x1000>; 163 interrupt-parent = <&gic>; 164 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; 165 clock-frequency = <400000>; /* Fast mode */ 166 #address-cells = <1>; 167 #size-cells = <0>; 168 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 169 clock-names = "i2cclk", "apb_pclk"; 170 resets = <&olb 0 16>; 171 i2c-transfer-timeout-us = <10000>; 172 mobileye,olb = <&olb 3>; 173 }; 174 175 i2c4: i2c@700000 { 176 compatible = "mobileye,eyeq5-i2c", "arm,primecell"; 177 reg = <0 0x700000 0x0 0x1000>; 178 interrupt-parent = <&gic>; 179 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>; 180 clock-frequency = <400000>; /* Fast mode */ 181 #address-cells = <1>; 182 #size-cells = <0>; 183 clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; 184 clock-names = "i2cclk", "apb_pclk"; 185 resets = <&olb 0 17>; 186 i2c-transfer-timeout-us = <10000>; 187 mobileye,olb = <&olb 4>; 188 }; 189 190 uart0: serial@800000 { 191 compatible = "arm,pl011", "arm,primecell"; 192 reg = <0 0x800000 0x0 0x1000>; 193 reg-io-width = <4>; 194 interrupt-parent = <&gic>; 195 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 197 clock-names = "uartclk", "apb_pclk"; 198 resets = <&olb 0 10>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&uart0_pins>; 201 }; 202 203 uart1: serial@900000 { 204 compatible = "arm,pl011", "arm,primecell"; 205 reg = <0 0x900000 0x0 0x1000>; 206 reg-io-width = <4>; 207 interrupt-parent = <&gic>; 208 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 210 clock-names = "uartclk", "apb_pclk"; 211 resets = <&olb 0 11>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&uart1_pins>; 214 }; 215 216 uart2: serial@a00000 { 217 compatible = "arm,pl011", "arm,primecell"; 218 reg = <0 0xa00000 0x0 0x1000>; 219 reg-io-width = <4>; 220 interrupt-parent = <&gic>; 221 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 223 clock-names = "uartclk", "apb_pclk"; 224 resets = <&olb 0 12>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&uart2_pins>; 227 }; 228 229 olb: system-controller@e00000 { 230 compatible = "mobileye,eyeq5-olb", "syscon"; 231 reg = <0 0xe00000 0x0 0x400>; 232 #reset-cells = <2>; 233 #clock-cells = <1>; 234 clocks = <&xtal>; 235 clock-names = "ref"; 236 #phy-cells = <1>; 237 }; 238 239 gic: interrupt-controller@140000 { 240 compatible = "mti,gic"; 241 reg = <0x0 0x140000 0x0 0x20000>; 242 interrupt-controller; 243 #interrupt-cells = <3>; 244 245 /* 246 * Declare the interrupt-parent even though the mti,gic 247 * binding doesn't require it, such that the kernel can 248 * figure out that cpu_intc is the root interrupt 249 * controller & should be probed first. 250 */ 251 interrupt-parent = <&cpu_intc>; 252 253 timer { 254 compatible = "mti,gic-timer"; 255 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 256 clocks = <&olb EQ5C_CPU_CORE0>; 257 }; 258 }; 259 260 emmc: mmc@2200000 { 261 compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc"; 262 reg = <0 0x2200000 0x0 0x1000>; 263 interrupt-parent = <&gic>; 264 interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&olb EQ5C_PER_EMMC>; 266 bus-width = <8>; 267 max-frequency = <200000000>; 268 mmc-ddr-1_8v; 269 sd-uhs-ddr50; 270 mmc-hs200-1_8v; 271 mmc-hs400-1_8v; 272 mmc-hs400-enhanced-strobe; 273 274 cdns,phy-input-delay-legacy = <4>; 275 cdns,phy-input-delay-mmc-highspeed = <2>; 276 cdns,phy-input-delay-mmc-ddr = <3>; 277 cdns,phy-dll-delay-sdclk = <32>; 278 cdns,phy-dll-delay-sdclk-hsmmc = <32>; 279 cdns,phy-dll-delay-strobe = <32>; 280 }; 281 282 gpio0: gpio@1400000 { 283 compatible = "mobileye,eyeq5-gpio"; 284 reg = <0x0 0x1400000 0x0 0x1000>; 285 gpio-bank = <0>; 286 ngpios = <29>; 287 interrupt-parent = <&gic>; 288 interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>; 289 gpio-controller; 290 #gpio-cells = <2>; 291 gpio-ranges = <&olb 0 0 29>; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 resets = <&olb 0 26>; 295 }; 296 297 gpio1: gpio@1500000 { 298 compatible = "mobileye,eyeq5-gpio"; 299 reg = <0x0 0x1500000 0x0 0x1000>; 300 gpio-bank = <1>; 301 ngpios = <23>; 302 interrupt-parent = <&gic>; 303 interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 gpio-ranges = <&olb 0 29 23>; 307 interrupt-controller; 308 #interrupt-cells = <2>; 309 resets = <&olb 0 26>; 310 }; 311 312 iocu-bus { 313 compatible = "simple-bus"; 314 #address-cells = <2>; 315 #size-cells = <2>; 316 ranges; 317 dma-coherent; 318 dma-ranges = <0x10 0x00000000 0x0 0x0 0x10 0>; 319 320 macb0: ethernet@2a00000 { 321 compatible = "mobileye,eyeq5-gem"; 322 reg = <0x0 0x02a00000 0x0 0x4000>; 323 interrupt-parent = <&gic>; 324 /* One interrupt per queue */ 325 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 329 clock-names = "pclk", "hclk", "tsu_clk"; 330 clocks = <&pclk>, <&pclk>, <&tsu_clk>; 331 nvmem-cells = <ð0_mac>; 332 nvmem-cell-names = "mac-address"; 333 phys = <&olb 0>; 334 }; 335 336 macb1: ethernet@2b00000 { 337 compatible = "mobileye,eyeq5-gem"; 338 reg = <0x0 0x02b00000 0x0 0x4000>; 339 interrupt-parent = <&gic>; 340 /* One interrupt per queue */ 341 interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; 345 clock-names = "pclk", "hclk", "tsu_clk"; 346 clocks = <&pclk>, <&pclk>, <&tsu_clk>; 347 nvmem-cells = <ð1_mac>; 348 nvmem-cell-names = "mac-address"; 349 phys = <&olb 1>; 350 }; 351 }; 352 353 }; 354}; 355 356#include "eyeq5-pins.dtsi" 357