1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2/* 3* Copyright 2023 Mobileye Vision Technologies Ltd. 4*/ 5 6#include <dt-bindings/interrupt-controller/mips-gic.h> 7 8#include <dt-bindings/clock/mobileye,eyeq5-clk.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "img,i6500"; 19 reg = <0>; 20 clocks = <&olb EQ5C_CPU_CORE0>; 21 }; 22 }; 23 24 reserved-memory { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 29 /* These reserved memory regions are also defined in bootmanager 30 * for configuring inbound translation for BARS, don't change 31 * these without syncing with bootmanager 32 */ 33 shmem0_reserved: shmem@804000000 { 34 reg = <0x8 0x04000000 0x0 0x1000000>; 35 }; 36 shmem1_reserved: shmem@805000000 { 37 reg = <0x8 0x05000000 0x0 0x1000000>; 38 }; 39 pci0_msi_reserved: pci0-msi@806000000 { 40 reg = <0x8 0x06000000 0x0 0x100000>; 41 }; 42 pci1_msi_reserved: pci1-msi@806100000 { 43 reg = <0x8 0x06100000 0x0 0x100000>; 44 }; 45 46 mini_coredump0_reserved: mini-coredump0@806200000 { 47 reg = <0x8 0x06200000 0x0 0x100000>; 48 }; 49 mhm_reserved_0: the-mhm-reserved-0@0 { 50 reg = <0x8 0x00000000 0x0 0x0000800>; 51 }; 52 }; 53 54 aliases { 55 serial0 = &uart0; 56 serial1 = &uart1; 57 serial2 = &uart2; 58 }; 59 60 cpu_intc: interrupt-controller { 61 compatible = "mti,cpu-interrupt-controller"; 62 interrupt-controller; 63 #address-cells = <0>; 64 #interrupt-cells = <1>; 65 }; 66 67 xtal: xtal { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <30000000>; 71 }; 72 73 pclk: pclk { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <250000000>; /* 250MHz */ 77 }; 78 79 tsu_clk: tsu-clk { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <125000000>; /* 125MHz */ 83 }; 84 85 soc: soc { 86 #address-cells = <2>; 87 #size-cells = <2>; 88 ranges; 89 compatible = "simple-bus"; 90 91 uart0: serial@800000 { 92 compatible = "arm,pl011", "arm,primecell"; 93 reg = <0 0x800000 0x0 0x1000>; 94 reg-io-width = <4>; 95 interrupt-parent = <&gic>; 96 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 98 clock-names = "uartclk", "apb_pclk"; 99 resets = <&olb 0 10>; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&uart0_pins>; 102 }; 103 104 uart1: serial@900000 { 105 compatible = "arm,pl011", "arm,primecell"; 106 reg = <0 0x900000 0x0 0x1000>; 107 reg-io-width = <4>; 108 interrupt-parent = <&gic>; 109 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 111 clock-names = "uartclk", "apb_pclk"; 112 resets = <&olb 0 11>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&uart1_pins>; 115 }; 116 117 uart2: serial@a00000 { 118 compatible = "arm,pl011", "arm,primecell"; 119 reg = <0 0xa00000 0x0 0x1000>; 120 reg-io-width = <4>; 121 interrupt-parent = <&gic>; 122 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; 123 clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; 124 clock-names = "uartclk", "apb_pclk"; 125 resets = <&olb 0 12>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&uart2_pins>; 128 }; 129 130 olb: system-controller@e00000 { 131 compatible = "mobileye,eyeq5-olb", "syscon"; 132 reg = <0 0xe00000 0x0 0x400>; 133 #reset-cells = <2>; 134 #clock-cells = <1>; 135 clocks = <&xtal>; 136 clock-names = "ref"; 137 }; 138 139 gic: interrupt-controller@140000 { 140 compatible = "mti,gic"; 141 reg = <0x0 0x140000 0x0 0x20000>; 142 interrupt-controller; 143 #interrupt-cells = <3>; 144 145 /* 146 * Declare the interrupt-parent even though the mti,gic 147 * binding doesn't require it, such that the kernel can 148 * figure out that cpu_intc is the root interrupt 149 * controller & should be probed first. 150 */ 151 interrupt-parent = <&cpu_intc>; 152 153 timer { 154 compatible = "mti,gic-timer"; 155 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 156 clocks = <&olb EQ5C_CPU_CORE0>; 157 }; 158 }; 159 }; 160}; 161 162#include "eyeq5-pins.dtsi" 163