xref: /linux/arch/mips/boot/dts/loongson/ls7a-pch.dtsi (revision 05909cd9a0c8811731b38697af13075e8954314f) 
1// SPDX-License-Identifier: GPL-2.0
2
3/ {
4	pch: bus@10000000 {
5		compatible = "simple-bus";
6		#address-cells = <2>;
7		#size-cells = <2>;
8		ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9				0 0x20000000 0 0x20000000 0 0x10000000
10				0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11				0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
12
13		pic: interrupt-controller@10000000 {
14			compatible = "loongson,pch-pic-1.0";
15			reg = <0 0x10000000 0 0x400>;
16			interrupt-controller;
17			interrupt-parent = <&htvec>;
18			loongson,pic-base-vec = <0>;
19			#interrupt-cells = <2>;
20		};
21
22		pci@1a000000 {
23			compatible = "loongson,ls7a-pci";
24			device_type = "pci";
25			#address-cells = <3>;
26			#size-cells = <2>;
27			#interrupt-cells = <2>;
28			msi-parent = <&msi>;
29
30			reg = <0 0x1a000000 0 0x02000000>,
31				<0xefe 0x00000000 0 0x20000000>;
32
33			ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
34				 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
35
36			ohci@4,0 {
37				compatible = "pci0014,7a24.0",
38						   "pci0014,7a24",
39						   "pciclass0c0310",
40						   "pciclass0c03";
41
42				reg = <0x2000 0x0 0x0 0x0 0x0>;
43				interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
44				interrupt-parent = <&pic>;
45			};
46
47			ehci@4,1 {
48				compatible = "pci0014,7a14.0",
49						   "pci0014,7a14",
50						   "pciclass0c0320",
51						   "pciclass0c03";
52
53				reg = <0x2100 0x0 0x0 0x0 0x0>;
54				interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
55				interrupt-parent = <&pic>;
56			};
57
58			ohci@5,0 {
59				compatible = "pci0014,7a24.0",
60						   "pci0014,7a24",
61						   "pciclass0c0310",
62						   "pciclass0c03";
63
64				reg = <0x2800 0x0 0x0 0x0 0x0>;
65				interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
66				interrupt-parent = <&pic>;
67			};
68
69			ehci@5,1 {
70				compatible = "pci0014,7a14.0",
71						   "pci0014,7a14",
72						   "pciclass0c0320",
73						   "pciclass0c03";
74
75				reg = <0x2900 0x0 0x0 0x0 0x0>;
76				interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
77				interrupt-parent = <&pic>;
78			};
79
80			sata@8,0 {
81				compatible = "pci0014,7a08.0",
82						   "pci0014,7a08",
83						   "pciclass010601",
84						   "pciclass0106";
85
86				reg = <0x4000 0x0 0x0 0x0 0x0>;
87				interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
88				interrupt-parent = <&pic>;
89			};
90
91			sata@8,1 {
92				compatible = "pci0014,7a08.0",
93						   "pci0014,7a08",
94						   "pciclass010601",
95						   "pciclass0106";
96
97				reg = <0x4100 0x0 0x0 0x0 0x0>;
98				interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
99				interrupt-parent = <&pic>;
100			};
101
102			sata@8,2 {
103				compatible = "pci0014,7a08.0",
104						   "pci0014,7a08",
105						   "pciclass010601",
106						   "pciclass0106";
107
108				reg = <0x4200 0x0 0x0 0x0 0x0>;
109				interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
110				interrupt-parent = <&pic>;
111			};
112
113			gpu@6,0 {
114				compatible = "pci0014,7a15.0",
115						   "pci0014,7a15",
116						   "pciclass030200",
117						   "pciclass0302";
118
119				reg = <0x3000 0x0 0x0 0x0 0x0>;
120				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
121				interrupt-parent = <&pic>;
122			};
123
124			dc@6,1 {
125				compatible = "pci0014,7a06.0",
126						   "pci0014,7a06",
127						   "pciclass030000",
128						   "pciclass0300";
129
130				reg = <0x3100 0x0 0x0 0x0 0x0>;
131				interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
132				interrupt-parent = <&pic>;
133			};
134
135			hda@7,0 {
136				compatible = "pci0014,7a07.0",
137						   "pci0014,7a07",
138						   "pciclass040300",
139						   "pciclass0403";
140
141				reg = <0x3800 0x0 0x0 0x0 0x0>;
142				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
143				interrupt-parent = <&pic>;
144			};
145
146			gmac@3,0 {
147				compatible = "pci0014,7a03.0",
148						   "pci0014,7a03",
149						   "pciclass020000",
150						   "pciclass0200";
151
152				reg = <0x1800 0x0 0x0 0x0 0x0>;
153				interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
154					     <13 IRQ_TYPE_LEVEL_HIGH>;
155				interrupt-names = "macirq", "eth_lpi";
156				interrupt-parent = <&pic>;
157				phy-mode = "rgmii";
158				mdio {
159					#address-cells = <1>;
160					#size-cells = <0>;
161					compatible = "snps,dwmac-mdio";
162					phy0: ethernet-phy@0 {
163						reg = <0>;
164					};
165				};
166			};
167
168			gmac@3,1 {
169				compatible = "pci0014,7a03.0",
170						   "pci0014,7a03",
171						   "pciclass020000",
172						   "pciclass0200";
173
174				reg = <0x1900 0x0 0x0 0x0 0x0>;
175				interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
176					     <15 IRQ_TYPE_LEVEL_HIGH>;
177				interrupt-names = "macirq", "eth_lpi";
178				interrupt-parent = <&pic>;
179				phy-mode = "rgmii";
180				mdio {
181					#address-cells = <1>;
182					#size-cells = <0>;
183					compatible = "snps,dwmac-mdio";
184					phy1: ethernet-phy@1 {
185						reg = <0>;
186					};
187				};
188			};
189
190			pci_bridge@9,0 {
191				compatible = "pci0014,7a19.1",
192						   "pci0014,7a19",
193						   "pciclass060400",
194						   "pciclass0604";
195
196				reg = <0x4800 0x0 0x0 0x0 0x0>;
197				interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
198				interrupt-parent = <&pic>;
199
200				#interrupt-cells = <1>;
201				interrupt-map-mask = <0 0 0 0>;
202				interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
203			};
204
205			pci_bridge@a,0 {
206				compatible = "pci0014,7a09.1",
207						   "pci0014,7a09",
208						   "pciclass060400",
209						   "pciclass0604";
210
211				reg = <0x5000 0x0 0x0 0x0 0x0>;
212				interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
213				interrupt-parent = <&pic>;
214
215				#interrupt-cells = <1>;
216				interrupt-map-mask = <0 0 0 0>;
217				interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
218			};
219
220			pci_bridge@b,0 {
221				compatible = "pci0014,7a09.1",
222						   "pci0014,7a09",
223						   "pciclass060400",
224						   "pciclass0604";
225
226				reg = <0x5800 0x0 0x0 0x0 0x0>;
227				interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
228				interrupt-parent = <&pic>;
229
230				#interrupt-cells = <1>;
231				interrupt-map-mask = <0 0 0 0>;
232				interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
233			};
234
235			pci_bridge@c,0 {
236				compatible = "pci0014,7a09.1",
237						   "pci0014,7a09",
238						   "pciclass060400",
239						   "pciclass0604";
240
241				reg = <0x6000 0x0 0x0 0x0 0x0>;
242				interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
243				interrupt-parent = <&pic>;
244
245				#interrupt-cells = <1>;
246				interrupt-map-mask = <0 0 0 0>;
247				interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
248			};
249
250			pci_bridge@d,0 {
251				compatible = "pci0014,7a19.1",
252						   "pci0014,7a19",
253						   "pciclass060400",
254						   "pciclass0604";
255
256				reg = <0x6800 0x0 0x0 0x0 0x0>;
257				interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
258				interrupt-parent = <&pic>;
259
260				#interrupt-cells = <1>;
261				interrupt-map-mask = <0 0 0 0>;
262				interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
263			};
264
265			pci_bridge@e,0 {
266				compatible = "pci0014,7a09.1",
267						   "pci0014,7a09",
268						   "pciclass060400",
269						   "pciclass0604";
270
271				reg = <0x7000 0x0 0x0 0x0 0x0>;
272				interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
273				interrupt-parent = <&pic>;
274
275				#interrupt-cells = <1>;
276				interrupt-map-mask = <0 0 0 0>;
277				interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
278			};
279
280			pci_bridge@f,0 {
281				compatible = "pci0014,7a29.1",
282						   "pci0014,7a29",
283						   "pciclass060400",
284						   "pciclass0604";
285
286				reg = <0x7800 0x0 0x0 0x0 0x0>;
287				interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
288				interrupt-parent = <&pic>;
289
290				#interrupt-cells = <1>;
291				interrupt-map-mask = <0 0 0 0>;
292				interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
293			};
294
295			pci_bridge@10,0 {
296				compatible = "pci0014,7a19.1",
297						   "pci0014,7a19",
298						   "pciclass060400",
299						   "pciclass0604";
300
301				reg = <0x8000 0x0 0x0 0x0 0x0>;
302				interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
303				interrupt-parent = <&pic>;
304
305				#interrupt-cells = <1>;
306				interrupt-map-mask = <0 0 0 0>;
307				interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
308			};
309
310			pci_bridge@11,0 {
311				compatible = "pci0014,7a29.1",
312						   "pci0014,7a29",
313						   "pciclass060400",
314						   "pciclass0604";
315
316				reg = <0x8800 0x0 0x0 0x0 0x0>;
317				interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
318				interrupt-parent = <&pic>;
319
320				#interrupt-cells = <1>;
321				interrupt-map-mask = <0 0 0 0>;
322				interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
323			};
324
325			pci_bridge@12,0 {
326				compatible = "pci0014,7a19.1",
327						   "pci0014,7a19",
328						   "pciclass060400",
329						   "pciclass0604";
330
331				reg = <0x9000 0x0 0x0 0x0 0x0>;
332				interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
333				interrupt-parent = <&pic>;
334
335				#interrupt-cells = <1>;
336				interrupt-map-mask = <0 0 0 0>;
337				interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
338			};
339
340			pci_bridge@13,0 {
341				compatible = "pci0014,7a29.1",
342						   "pci0014,7a29",
343						   "pciclass060400",
344						   "pciclass0604";
345
346				reg = <0x9800 0x0 0x0 0x0 0x0>;
347				interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
348				interrupt-parent = <&pic>;
349
350				#interrupt-cells = <1>;
351				interrupt-map-mask = <0 0 0 0>;
352				interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
353			};
354
355			pci_bridge@14,0 {
356				compatible = "pci0014,7a19.1",
357						   "pci0014,7a19",
358						   "pciclass060400",
359						   "pciclass0604";
360
361				reg = <0xa000 0x0 0x0 0x0 0x0>;
362				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
363				interrupt-parent = <&pic>;
364
365				#interrupt-cells = <1>;
366				interrupt-map-mask = <0 0 0 0>;
367				interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
368			};
369		};
370
371		isa {
372			compatible = "isa";
373			#address-cells = <2>;
374			#size-cells = <1>;
375			ranges = <1 0 0 0x18000000 0x20000>;
376		};
377	};
378};
379