1// SPDX-License-Identifier: GPL-2.0 2 3/dts-v1/; 4 5#include <dt-bindings/interrupt-controller/irq.h> 6 7/ { 8 compatible = "loongson,loongson2k1000"; 9 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 device_type = "cpu"; 19 compatible = "loongson,gs264"; 20 reg = <0x0>; 21 #clock-cells = <1>; 22 clocks = <&cpu_clk>; 23 }; 24 }; 25 26 cpu_clk: cpu_clk { 27 #clock-cells = <0>; 28 compatible = "fixed-clock"; 29 clock-frequency = <800000000>; 30 }; 31 32 cpuintc: interrupt-controller { 33 #address-cells = <0>; 34 #interrupt-cells = <1>; 35 interrupt-controller; 36 compatible = "mti,cpu-interrupt-controller"; 37 }; 38 39 package0: bus@10000000 { 40 compatible = "simple-bus"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */ 44 0 0x40000000 0 0x40000000 0 0x40000000 45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>; 46 47 isa@18000000 { 48 compatible = "isa"; 49 #size-cells = <1>; 50 #address-cells = <2>; 51 ranges = <1 0x0 0x0 0x18000000 0x4000>; 52 }; 53 54 pm: reset-controller@1fe07000 { 55 compatible = "loongson,ls2k-pm"; 56 reg = <0 0x1fe07000 0 0x422>; 57 }; 58 59 liointc0: interrupt-controller@1fe11400 { 60 compatible = "loongson,liointc-2.0"; 61 reg = <0 0x1fe11400 0 0x40>, 62 <0 0x1fe11040 0 0x8>, 63 <0 0x1fe11140 0 0x8>; 64 reg-names = "main", "isr0", "isr1"; 65 66 interrupt-controller; 67 #interrupt-cells = <2>; 68 69 interrupt-parent = <&cpuintc>; 70 interrupts = <2>; 71 interrupt-names = "int0"; 72 73 loongson,parent_int_map = <0xffffffff>, /* int0 */ 74 <0x00000000>, /* int1 */ 75 <0x00000000>, /* int2 */ 76 <0x00000000>; /* int3 */ 77 }; 78 79 liointc1: interrupt-controller@1fe11440 { 80 compatible = "loongson,liointc-2.0"; 81 reg = <0 0x1fe11440 0 0x40>, 82 <0 0x1fe11048 0 0x8>, 83 <0 0x1fe11148 0 0x8>; 84 reg-names = "main", "isr0", "isr1"; 85 86 interrupt-controller; 87 #interrupt-cells = <2>; 88 89 interrupt-parent = <&cpuintc>; 90 interrupts = <3>; 91 interrupt-names = "int1"; 92 93 loongson,parent_int_map = <0x00000000>, /* int0 */ 94 <0xffffffff>, /* int1 */ 95 <0x00000000>, /* int2 */ 96 <0x00000000>; /* int3 */ 97 }; 98 99 rtc0: rtc@1fe07800 { 100 compatible = "loongson,ls2k1000-rtc"; 101 reg = <0 0x1fe07800 0 0x78>; 102 interrupt-parent = <&liointc1>; 103 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 104 }; 105 106 uart0: serial@1fe00000 { 107 compatible = "ns16550a"; 108 reg = <0 0x1fe00000 0 0x8>; 109 clock-frequency = <125000000>; 110 interrupt-parent = <&liointc0>; 111 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 112 no-loopback-test; 113 }; 114 115 pci@1a000000 { 116 compatible = "loongson,ls2k-pci"; 117 device_type = "pci"; 118 #address-cells = <3>; 119 #size-cells = <2>; 120 121 reg = <0 0x1a000000 0 0x02000000>, 122 <0xfe 0x00000000 0 0x20000000>; 123 124 ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000 0x0 0x00010000>, 125 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 126 127 gmac@3,0 { 128 compatible = "pci0014,7a03.0", 129 "pci0014,7a03", 130 "pciclass0c0320", 131 "pciclass0c03"; 132 133 reg = <0x1800 0x0 0x0 0x0 0x0>; 134 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, 135 <13 IRQ_TYPE_LEVEL_HIGH>; 136 interrupt-names = "macirq", "eth_lpi"; 137 interrupt-parent = <&liointc0>; 138 phy-mode = "rgmii-id"; 139 phy-handle = <&phy1>; 140 mdio { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 compatible = "snps,dwmac-mdio"; 144 phy0: ethernet-phy@0 { 145 reg = <0>; 146 }; 147 }; 148 }; 149 150 gmac@3,1 { 151 compatible = "pci0014,7a03.0", 152 "pci0014,7a03", 153 "pciclass0c0320", 154 "pciclass0c03", 155 "loongson, pci-gmac"; 156 157 reg = <0x1900 0x0 0x0 0x0 0x0>; 158 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 159 <15 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-names = "macirq", "eth_lpi"; 161 interrupt-parent = <&liointc0>; 162 phy-mode = "rgmii-id"; 163 phy-handle = <&phy1>; 164 mdio { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 compatible = "snps,dwmac-mdio"; 168 phy1: ethernet-phy@1 { 169 reg = <0>; 170 }; 171 }; 172 }; 173 174 ehci@4,1 { 175 compatible = "pci0014,7a14.0", 176 "pci0014,7a14", 177 "pciclass0c0320", 178 "pciclass0c03"; 179 180 reg = <0x2100 0x0 0x0 0x0 0x0>; 181 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 182 interrupt-parent = <&liointc1>; 183 }; 184 185 ohci@4,2 { 186 compatible = "pci0014,7a24.0", 187 "pci0014,7a24", 188 "pciclass0c0310", 189 "pciclass0c03"; 190 191 reg = <0x2200 0x0 0x0 0x0 0x0>; 192 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-parent = <&liointc1>; 194 }; 195 196 sata@8,0 { 197 compatible = "pci0014,7a08.0", 198 "pci0014,7a08", 199 "pciclass010601", 200 "pciclass0106"; 201 202 reg = <0x4000 0x0 0x0 0x0 0x0>; 203 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 204 interrupt-parent = <&liointc0>; 205 }; 206 207 pcie@9,0 { 208 compatible = "pci0014,7a19.0", 209 "pci0014,7a19", 210 "pciclass060400", 211 "pciclass0604"; 212 213 reg = <0x4800 0x0 0x0 0x0 0x0>; 214 #address-cells = <3>; 215 #size-cells = <2>; 216 device_type = "pci"; 217 #interrupt-cells = <1>; 218 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 219 interrupt-parent = <&liointc1>; 220 interrupt-map-mask = <0 0 0 0>; 221 interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_HIGH>; 222 ranges; 223 external-facing; 224 }; 225 226 pcie@a,0 { 227 compatible = "pci0014,7a09.0", 228 "pci0014,7a09", 229 "pciclass060400", 230 "pciclass0604"; 231 232 reg = <0x5000 0x0 0x0 0x0 0x0>; 233 #address-cells = <3>; 234 #size-cells = <2>; 235 device_type = "pci"; 236 #interrupt-cells = <1>; 237 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-parent = <&liointc1>; 239 interrupt-map-mask = <0 0 0 0>; 240 interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>; 241 ranges; 242 external-facing; 243 }; 244 245 pcie@b,0 { 246 compatible = "pci0014,7a09.0", 247 "pci0014,7a09", 248 "pciclass060400", 249 "pciclass0604"; 250 251 reg = <0x5800 0x0 0x0 0x0 0x0>; 252 #address-cells = <3>; 253 #size-cells = <2>; 254 device_type = "pci"; 255 #interrupt-cells = <1>; 256 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-parent = <&liointc1>; 258 interrupt-map-mask = <0 0 0 0>; 259 interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>; 260 ranges; 261 external-facing; 262 }; 263 264 pcie@c,0 { 265 compatible = "pci0014,7a09.0", 266 "pci0014,7a09", 267 "pciclass060400", 268 "pciclass0604"; 269 270 reg = <0x6000 0x0 0x0 0x0 0x0>; 271 #address-cells = <3>; 272 #size-cells = <2>; 273 device_type = "pci"; 274 #interrupt-cells = <1>; 275 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-parent = <&liointc1>; 277 interrupt-map-mask = <0 0 0 0>; 278 interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>; 279 ranges; 280 external-facing; 281 }; 282 283 pcie@d,0 { 284 compatible = "pci0014,7a19.0", 285 "pci0014,7a19", 286 "pciclass060400", 287 "pciclass0604"; 288 289 reg = <0x6800 0x0 0x0 0x0 0x0>; 290 #address-cells = <3>; 291 #size-cells = <2>; 292 device_type = "pci"; 293 #interrupt-cells = <1>; 294 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 295 interrupt-parent = <&liointc1>; 296 interrupt-map-mask = <0 0 0 0>; 297 interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>; 298 ranges; 299 external-facing; 300 }; 301 302 pcie@e,0 { 303 compatible = "pci0014,7a09.0", 304 "pci0014,7a09", 305 "pciclass060400", 306 "pciclass0604"; 307 308 reg = <0x7000 0x0 0x0 0x0 0x0>; 309 #address-cells = <3>; 310 #size-cells = <2>; 311 device_type = "pci"; 312 #interrupt-cells = <1>; 313 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-parent = <&liointc1>; 315 interrupt-map-mask = <0 0 0 0>; 316 interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>; 317 ranges; 318 external-facing; 319 }; 320 321 }; 322 }; 323}; 324 325