xref: /linux/arch/mips/boot/dts/ingenic/jz4780.dtsi (revision bdd1a21b52557ea8f61d0a5dc2f77151b576eb70) 
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4780-cgu.h>
3#include <dt-bindings/clock/ingenic,tcu.h>
4#include <dt-bindings/dma/jz4780-dma.h>
5
6/ {
7	#address-cells = <1>;
8	#size-cells = <1>;
9	compatible = "ingenic,jz4780";
10
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18			reg = <0>;
19
20			clocks = <&cgu JZ4780_CLK_CPU>;
21			clock-names = "cpu";
22		};
23
24		cpu1: cpu@1 {
25			device_type = "cpu";
26			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
27			reg = <1>;
28
29			clocks = <&cgu JZ4780_CLK_CORE1>;
30			clock-names = "cpu";
31		};
32	};
33
34	cpuintc: interrupt-controller {
35		#address-cells = <0>;
36		#interrupt-cells = <1>;
37		interrupt-controller;
38		compatible = "mti,cpu-interrupt-controller";
39	};
40
41	intc: interrupt-controller@10001000 {
42		compatible = "ingenic,jz4780-intc";
43		reg = <0x10001000 0x50>;
44
45		interrupt-controller;
46		#interrupt-cells = <1>;
47
48		interrupt-parent = <&cpuintc>;
49		interrupts = <2>;
50	};
51
52	ext: ext {
53		compatible = "fixed-clock";
54		#clock-cells = <0>;
55	};
56
57	rtc: rtc {
58		compatible = "fixed-clock";
59		#clock-cells = <0>;
60		clock-frequency = <32768>;
61	};
62
63	cgu: jz4780-cgu@10000000 {
64		compatible = "ingenic,jz4780-cgu", "simple-mfd";
65		reg = <0x10000000 0x100>;
66		#address-cells = <1>;
67		#size-cells = <1>;
68		ranges = <0x0 0x10000000 0x100>;
69
70		#clock-cells = <1>;
71
72		clocks = <&ext>, <&rtc>;
73		clock-names = "ext", "rtc";
74
75		otg_phy: usb-phy@3c {
76			compatible = "ingenic,jz4780-phy";
77			reg = <0x3c 0x10>;
78
79			clocks = <&cgu JZ4780_CLK_OTG1>;
80
81			#phy-cells = <0>;
82
83			status = "disabled";
84		};
85
86		rng: rng@d8 {
87			compatible = "ingenic,jz4780-rng";
88			reg = <0xd8 0x8>;
89
90			status = "disabled";
91		};
92	};
93
94	tcu: timer@10002000 {
95		compatible = "ingenic,jz4780-tcu",
96			     "ingenic,jz4770-tcu",
97			     "simple-mfd";
98		reg = <0x10002000 0x1000>;
99		#address-cells = <1>;
100		#size-cells = <1>;
101		ranges = <0x0 0x10002000 0x1000>;
102
103		#clock-cells = <1>;
104
105		clocks = <&cgu JZ4780_CLK_RTCLK>,
106			 <&cgu JZ4780_CLK_EXCLK>,
107			 <&cgu JZ4780_CLK_PCLK>;
108		clock-names = "rtc", "ext", "pclk";
109
110		interrupt-controller;
111		#interrupt-cells = <1>;
112
113		interrupt-parent = <&intc>;
114		interrupts = <27 26 25>;
115
116		watchdog: watchdog@0 {
117			compatible = "ingenic,jz4780-watchdog";
118			reg = <0x0 0xc>;
119
120			clocks = <&tcu TCU_CLK_WDT>;
121			clock-names = "wdt";
122		};
123
124		pwm: pwm@40 {
125			compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm";
126			reg = <0x40 0x80>;
127
128			#pwm-cells = <3>;
129
130			clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
131				 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
132				 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
133				 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
134			clock-names = "timer0", "timer1", "timer2", "timer3",
135				      "timer4", "timer5", "timer6", "timer7";
136		};
137
138		ost: timer@e0 {
139			compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost";
140			reg = <0xe0 0x20>;
141
142			clocks = <&tcu TCU_CLK_OST>;
143			clock-names = "ost";
144
145			interrupts = <15>;
146		};
147	};
148
149	rtc_dev: rtc@10003000 {
150		compatible = "ingenic,jz4780-rtc";
151		reg = <0x10003000 0x4c>;
152
153		interrupt-parent = <&intc>;
154		interrupts = <32>;
155
156		clocks = <&cgu JZ4780_CLK_RTCLK>;
157		clock-names = "rtc";
158	};
159
160	pinctrl: pin-controller@10010000 {
161		compatible = "ingenic,jz4780-pinctrl";
162		reg = <0x10010000 0x600>;
163
164		#address-cells = <1>;
165		#size-cells = <0>;
166
167		gpa: gpio@0 {
168			compatible = "ingenic,jz4780-gpio";
169			reg = <0>;
170
171			gpio-controller;
172			gpio-ranges = <&pinctrl 0 0 32>;
173			#gpio-cells = <2>;
174
175			interrupt-controller;
176			#interrupt-cells = <2>;
177
178			interrupt-parent = <&intc>;
179			interrupts = <17>;
180		};
181
182		gpb: gpio@1 {
183			compatible = "ingenic,jz4780-gpio";
184			reg = <1>;
185
186			gpio-controller;
187			gpio-ranges = <&pinctrl 0 32 32>;
188			#gpio-cells = <2>;
189
190			interrupt-controller;
191			#interrupt-cells = <2>;
192
193			interrupt-parent = <&intc>;
194			interrupts = <16>;
195		};
196
197		gpc: gpio@2 {
198			compatible = "ingenic,jz4780-gpio";
199			reg = <2>;
200
201			gpio-controller;
202			gpio-ranges = <&pinctrl 0 64 32>;
203			#gpio-cells = <2>;
204
205			interrupt-controller;
206			#interrupt-cells = <2>;
207
208			interrupt-parent = <&intc>;
209			interrupts = <15>;
210		};
211
212		gpd: gpio@3 {
213			compatible = "ingenic,jz4780-gpio";
214			reg = <3>;
215
216			gpio-controller;
217			gpio-ranges = <&pinctrl 0 96 32>;
218			#gpio-cells = <2>;
219
220			interrupt-controller;
221			#interrupt-cells = <2>;
222
223			interrupt-parent = <&intc>;
224			interrupts = <14>;
225		};
226
227		gpe: gpio@4 {
228			compatible = "ingenic,jz4780-gpio";
229			reg = <4>;
230
231			gpio-controller;
232			gpio-ranges = <&pinctrl 0 128 32>;
233			#gpio-cells = <2>;
234
235			interrupt-controller;
236			#interrupt-cells = <2>;
237
238			interrupt-parent = <&intc>;
239			interrupts = <13>;
240		};
241
242		gpf: gpio@5 {
243			compatible = "ingenic,jz4780-gpio";
244			reg = <5>;
245
246			gpio-controller;
247			gpio-ranges = <&pinctrl 0 160 32>;
248			#gpio-cells = <2>;
249
250			interrupt-controller;
251			#interrupt-cells = <2>;
252
253			interrupt-parent = <&intc>;
254			interrupts = <12>;
255		};
256	};
257
258	spi_gpio {
259		compatible = "spi-gpio";
260		#address-cells = <1>;
261		#size-cells = <0>;
262		num-chipselects = <2>;
263
264		gpio-miso = <&gpe 14 0>;
265		gpio-sck = <&gpe 15 0>;
266		gpio-mosi = <&gpe 17 0>;
267		cs-gpios = <&gpe 16 0>, <&gpe 18 0>;
268
269		spidev@0 {
270			compatible = "spidev";
271			reg = <0>;
272			spi-max-frequency = <1000000>;
273		};
274	};
275
276	uart0: serial@10030000 {
277		compatible = "ingenic,jz4780-uart";
278		reg = <0x10030000 0x100>;
279
280		interrupt-parent = <&intc>;
281		interrupts = <51>;
282
283		clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
284		clock-names = "baud", "module";
285
286		status = "disabled";
287	};
288
289	uart1: serial@10031000 {
290		compatible = "ingenic,jz4780-uart";
291		reg = <0x10031000 0x100>;
292
293		interrupt-parent = <&intc>;
294		interrupts = <50>;
295
296		clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
297		clock-names = "baud", "module";
298
299		status = "disabled";
300	};
301
302	uart2: serial@10032000 {
303		compatible = "ingenic,jz4780-uart";
304		reg = <0x10032000 0x100>;
305
306		interrupt-parent = <&intc>;
307		interrupts = <49>;
308
309		clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
310		clock-names = "baud", "module";
311
312		status = "disabled";
313	};
314
315	uart3: serial@10033000 {
316		compatible = "ingenic,jz4780-uart";
317		reg = <0x10033000 0x100>;
318
319		interrupt-parent = <&intc>;
320		interrupts = <48>;
321
322		clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
323		clock-names = "baud", "module";
324
325		status = "disabled";
326	};
327
328	uart4: serial@10034000 {
329		compatible = "ingenic,jz4780-uart";
330		reg = <0x10034000 0x100>;
331
332		interrupt-parent = <&intc>;
333		interrupts = <34>;
334
335		clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
336		clock-names = "baud", "module";
337
338		status = "disabled";
339	};
340
341	i2c0: i2c@10050000 {
342		compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
343		#address-cells = <1>;
344		#size-cells = <0>;
345
346		reg = <0x10050000 0x1000>;
347
348		interrupt-parent = <&intc>;
349		interrupts = <60>;
350
351		clocks = <&cgu JZ4780_CLK_SMB0>;
352		clock-frequency = <100000>;
353		pinctrl-names = "default";
354		pinctrl-0 = <&pins_i2c0_data>;
355
356		status = "disabled";
357	};
358
359	i2c1: i2c@10051000 {
360		compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
361		#address-cells = <1>;
362		#size-cells = <0>;
363		reg = <0x10051000 0x1000>;
364
365		interrupt-parent = <&intc>;
366		interrupts = <59>;
367
368		clocks = <&cgu JZ4780_CLK_SMB1>;
369		clock-frequency = <100000>;
370		pinctrl-names = "default";
371		pinctrl-0 = <&pins_i2c1_data>;
372
373		status = "disabled";
374	};
375
376	i2c2: i2c@10052000 {
377		compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
378		#address-cells = <1>;
379		#size-cells = <0>;
380		reg = <0x10052000 0x1000>;
381
382		interrupt-parent = <&intc>;
383		interrupts = <58>;
384
385		clocks = <&cgu JZ4780_CLK_SMB2>;
386		clock-frequency = <100000>;
387		pinctrl-names = "default";
388		pinctrl-0 = <&pins_i2c2_data>;
389
390		status = "disabled";
391	};
392
393	i2c3: i2c@10053000 {
394		compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
395		#address-cells = <1>;
396		#size-cells = <0>;
397		reg = <0x10053000 0x1000>;
398
399		interrupt-parent = <&intc>;
400		interrupts = <57>;
401
402		clocks = <&cgu JZ4780_CLK_SMB3>;
403		clock-frequency = <100000>;
404		pinctrl-names = "default";
405		pinctrl-0 = <&pins_i2c3_data>;
406
407		status = "disabled";
408	};
409
410	i2c4: i2c@10054000 {
411		compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
412		#address-cells = <1>;
413		#size-cells = <0>;
414		reg = <0x10054000 0x1000>;
415
416		interrupt-parent = <&intc>;
417		interrupts = <56>;
418
419		clocks = <&cgu JZ4780_CLK_SMB4>;
420		clock-frequency = <100000>;
421		pinctrl-names = "default";
422		pinctrl-0 = <&pins_i2c4_data>;
423
424		status = "disabled";
425	};
426
427	nemc: nemc@13410000 {
428		compatible = "ingenic,jz4780-nemc", "simple-mfd";
429		reg = <0x13410000 0x10000>;
430		#address-cells = <2>;
431		#size-cells = <1>;
432		ranges = <0 0 0x13410000 0x10000>,
433			 <1 0 0x1b000000 0x1000000>,
434			 <2 0 0x1a000000 0x1000000>,
435			 <3 0 0x19000000 0x1000000>,
436			 <4 0 0x18000000 0x1000000>,
437			 <5 0 0x17000000 0x1000000>,
438			 <6 0 0x16000000 0x1000000>;
439
440		clocks = <&cgu JZ4780_CLK_NEMC>;
441
442		status = "disabled";
443
444		efuse: efuse@d0 {
445			reg = <0 0xd0 0x30>;
446			compatible = "ingenic,jz4780-efuse";
447
448			clocks = <&cgu JZ4780_CLK_AHB2>;
449
450			#address-cells = <1>;
451			#size-cells = <1>;
452
453			eth0_addr: eth-mac-addr@0x22 {
454				reg = <0x22 0x6>;
455			};
456		};
457	};
458
459	dma: dma@13420000 {
460		compatible = "ingenic,jz4780-dma";
461		reg = <0x13420000 0x400>, <0x13421000 0x40>;
462		#dma-cells = <2>;
463
464		interrupt-parent = <&intc>;
465		interrupts = <10>;
466
467		clocks = <&cgu JZ4780_CLK_PDMA>;
468	};
469
470	mmc0: mmc@13450000 {
471		compatible = "ingenic,jz4780-mmc";
472		reg = <0x13450000 0x1000>;
473
474		interrupt-parent = <&intc>;
475		interrupts = <37>;
476
477		clocks = <&cgu JZ4780_CLK_MSC0>;
478		clock-names = "mmc";
479
480		cap-sd-highspeed;
481		cap-mmc-highspeed;
482		cap-sdio-irq;
483		dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
484		       <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
485		dma-names = "rx", "tx";
486
487		status = "disabled";
488	};
489
490	mmc1: mmc@13460000 {
491		compatible = "ingenic,jz4780-mmc";
492		reg = <0x13460000 0x1000>;
493
494		interrupt-parent = <&intc>;
495		interrupts = <36>;
496
497		clocks = <&cgu JZ4780_CLK_MSC1>;
498		clock-names = "mmc";
499
500		cap-sd-highspeed;
501		cap-mmc-highspeed;
502		cap-sdio-irq;
503		dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
504		       <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
505		dma-names = "rx", "tx";
506
507		status = "disabled";
508	};
509
510	bch: bch@134d0000 {
511		compatible = "ingenic,jz4780-bch";
512		reg = <0x134d0000 0x10000>;
513
514		clocks = <&cgu JZ4780_CLK_BCH>;
515
516		status = "disabled";
517	};
518
519	otg: usb@13500000 {
520		compatible = "ingenic,jz4780-otg", "snps,dwc2";
521		reg = <0x13500000 0x40000>;
522
523		interrupt-parent = <&intc>;
524		interrupts = <21>;
525
526		clocks = <&cgu JZ4780_CLK_UHC>;
527		clock-names = "otg";
528
529		phys = <&otg_phy>;
530		phy-names = "usb2-phy";
531
532		g-rx-fifo-size = <768>;
533		g-np-tx-fifo-size = <256>;
534		g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
535
536		status = "disabled";
537	};
538};
539