1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/jz4780-cgu.h> 3#include <dt-bindings/clock/ingenic,tcu.h> 4#include <dt-bindings/dma/jz4780-dma.h> 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "ingenic,jz4780"; 10 11 cpuintc: interrupt-controller { 12 #address-cells = <0>; 13 #interrupt-cells = <1>; 14 interrupt-controller; 15 compatible = "mti,cpu-interrupt-controller"; 16 }; 17 18 intc: interrupt-controller@10001000 { 19 compatible = "ingenic,jz4780-intc"; 20 reg = <0x10001000 0x50>; 21 22 interrupt-controller; 23 #interrupt-cells = <1>; 24 25 interrupt-parent = <&cpuintc>; 26 interrupts = <2>; 27 }; 28 29 ext: ext { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 }; 33 34 rtc: rtc { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32768>; 38 }; 39 40 cgu: jz4780-cgu@10000000 { 41 compatible = "ingenic,jz4780-cgu"; 42 reg = <0x10000000 0x100>; 43 44 clocks = <&ext>, <&rtc>; 45 clock-names = "ext", "rtc"; 46 47 #clock-cells = <1>; 48 }; 49 50 tcu: timer@10002000 { 51 compatible = "ingenic,jz4780-tcu", 52 "ingenic,jz4770-tcu", 53 "simple-mfd"; 54 reg = <0x10002000 0x1000>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges = <0x0 0x10002000 0x1000>; 58 59 #clock-cells = <1>; 60 61 clocks = <&cgu JZ4780_CLK_RTCLK>, 62 <&cgu JZ4780_CLK_EXCLK>, 63 <&cgu JZ4780_CLK_PCLK>; 64 clock-names = "rtc", "ext", "pclk"; 65 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 69 interrupt-parent = <&intc>; 70 interrupts = <27 26 25>; 71 72 watchdog: watchdog@0 { 73 compatible = "ingenic,jz4780-watchdog"; 74 reg = <0x0 0xc>; 75 76 clocks = <&tcu TCU_CLK_WDT>; 77 clock-names = "wdt"; 78 }; 79 80 pwm: pwm@40 { 81 compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm"; 82 reg = <0x40 0x80>; 83 84 #pwm-cells = <3>; 85 86 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, 87 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, 88 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, 89 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; 90 clock-names = "timer0", "timer1", "timer2", "timer3", 91 "timer4", "timer5", "timer6", "timer7"; 92 }; 93 94 ost: timer@e0 { 95 compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost"; 96 reg = <0xe0 0x20>; 97 98 clocks = <&tcu TCU_CLK_OST>; 99 clock-names = "ost"; 100 101 interrupts = <15>; 102 }; 103 }; 104 105 rtc_dev: rtc@10003000 { 106 compatible = "ingenic,jz4780-rtc"; 107 reg = <0x10003000 0x4c>; 108 109 interrupt-parent = <&intc>; 110 interrupts = <32>; 111 112 clocks = <&cgu JZ4780_CLK_RTCLK>; 113 clock-names = "rtc"; 114 }; 115 116 pinctrl: pin-controller@10010000 { 117 compatible = "ingenic,jz4780-pinctrl"; 118 reg = <0x10010000 0x600>; 119 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 gpa: gpio@0 { 124 compatible = "ingenic,jz4780-gpio"; 125 reg = <0>; 126 127 gpio-controller; 128 gpio-ranges = <&pinctrl 0 0 32>; 129 #gpio-cells = <2>; 130 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 134 interrupt-parent = <&intc>; 135 interrupts = <17>; 136 }; 137 138 gpb: gpio@1 { 139 compatible = "ingenic,jz4780-gpio"; 140 reg = <1>; 141 142 gpio-controller; 143 gpio-ranges = <&pinctrl 0 32 32>; 144 #gpio-cells = <2>; 145 146 interrupt-controller; 147 #interrupt-cells = <2>; 148 149 interrupt-parent = <&intc>; 150 interrupts = <16>; 151 }; 152 153 gpc: gpio@2 { 154 compatible = "ingenic,jz4780-gpio"; 155 reg = <2>; 156 157 gpio-controller; 158 gpio-ranges = <&pinctrl 0 64 32>; 159 #gpio-cells = <2>; 160 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 164 interrupt-parent = <&intc>; 165 interrupts = <15>; 166 }; 167 168 gpd: gpio@3 { 169 compatible = "ingenic,jz4780-gpio"; 170 reg = <3>; 171 172 gpio-controller; 173 gpio-ranges = <&pinctrl 0 96 32>; 174 #gpio-cells = <2>; 175 176 interrupt-controller; 177 #interrupt-cells = <2>; 178 179 interrupt-parent = <&intc>; 180 interrupts = <14>; 181 }; 182 183 gpe: gpio@4 { 184 compatible = "ingenic,jz4780-gpio"; 185 reg = <4>; 186 187 gpio-controller; 188 gpio-ranges = <&pinctrl 0 128 32>; 189 #gpio-cells = <2>; 190 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 194 interrupt-parent = <&intc>; 195 interrupts = <13>; 196 }; 197 198 gpf: gpio@5 { 199 compatible = "ingenic,jz4780-gpio"; 200 reg = <5>; 201 202 gpio-controller; 203 gpio-ranges = <&pinctrl 0 160 32>; 204 #gpio-cells = <2>; 205 206 interrupt-controller; 207 #interrupt-cells = <2>; 208 209 interrupt-parent = <&intc>; 210 interrupts = <12>; 211 }; 212 }; 213 214 spi_gpio { 215 compatible = "spi-gpio"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 num-chipselects = <2>; 219 220 gpio-miso = <&gpe 14 0>; 221 gpio-sck = <&gpe 15 0>; 222 gpio-mosi = <&gpe 17 0>; 223 cs-gpios = <&gpe 16 0>, <&gpe 18 0>; 224 225 spidev@0 { 226 compatible = "spidev"; 227 reg = <0>; 228 spi-max-frequency = <1000000>; 229 }; 230 }; 231 232 uart0: serial@10030000 { 233 compatible = "ingenic,jz4780-uart"; 234 reg = <0x10030000 0x100>; 235 236 interrupt-parent = <&intc>; 237 interrupts = <51>; 238 239 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>; 240 clock-names = "baud", "module"; 241 242 status = "disabled"; 243 }; 244 245 uart1: serial@10031000 { 246 compatible = "ingenic,jz4780-uart"; 247 reg = <0x10031000 0x100>; 248 249 interrupt-parent = <&intc>; 250 interrupts = <50>; 251 252 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>; 253 clock-names = "baud", "module"; 254 255 status = "disabled"; 256 }; 257 258 uart2: serial@10032000 { 259 compatible = "ingenic,jz4780-uart"; 260 reg = <0x10032000 0x100>; 261 262 interrupt-parent = <&intc>; 263 interrupts = <49>; 264 265 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; 266 clock-names = "baud", "module"; 267 268 status = "disabled"; 269 }; 270 271 uart3: serial@10033000 { 272 compatible = "ingenic,jz4780-uart"; 273 reg = <0x10033000 0x100>; 274 275 interrupt-parent = <&intc>; 276 interrupts = <48>; 277 278 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>; 279 clock-names = "baud", "module"; 280 281 status = "disabled"; 282 }; 283 284 uart4: serial@10034000 { 285 compatible = "ingenic,jz4780-uart"; 286 reg = <0x10034000 0x100>; 287 288 interrupt-parent = <&intc>; 289 interrupts = <34>; 290 291 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>; 292 clock-names = "baud", "module"; 293 294 status = "disabled"; 295 }; 296 297 i2c0: i2c@10050000 { 298 compatible = "ingenic,jz4780-i2c"; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 302 reg = <0x10050000 0x1000>; 303 304 interrupt-parent = <&intc>; 305 interrupts = <60>; 306 307 clocks = <&cgu JZ4780_CLK_SMB0>; 308 clock-frequency = <100000>; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pins_i2c0_data>; 311 312 status = "disabled"; 313 }; 314 315 i2c1: i2c@10051000 { 316 compatible = "ingenic,jz4780-i2c"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg = <0x10051000 0x1000>; 320 321 interrupt-parent = <&intc>; 322 interrupts = <59>; 323 324 clocks = <&cgu JZ4780_CLK_SMB1>; 325 clock-frequency = <100000>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pins_i2c1_data>; 328 329 status = "disabled"; 330 }; 331 332 i2c2: i2c@10052000 { 333 compatible = "ingenic,jz4780-i2c"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <0x10052000 0x1000>; 337 338 interrupt-parent = <&intc>; 339 interrupts = <58>; 340 341 clocks = <&cgu JZ4780_CLK_SMB2>; 342 clock-frequency = <100000>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pins_i2c2_data>; 345 346 status = "disabled"; 347 }; 348 349 i2c3: i2c@10053000 { 350 compatible = "ingenic,jz4780-i2c"; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 reg = <0x10053000 0x1000>; 354 355 interrupt-parent = <&intc>; 356 interrupts = <57>; 357 358 clocks = <&cgu JZ4780_CLK_SMB3>; 359 clock-frequency = <100000>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pins_i2c3_data>; 362 363 status = "disabled"; 364 }; 365 366 i2c4: i2c@10054000 { 367 compatible = "ingenic,jz4780-i2c"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <0x10054000 0x1000>; 371 372 interrupt-parent = <&intc>; 373 interrupts = <56>; 374 375 clocks = <&cgu JZ4780_CLK_SMB4>; 376 clock-frequency = <100000>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pins_i2c4_data>; 379 380 status = "disabled"; 381 }; 382 383 nemc: nemc@13410000 { 384 compatible = "ingenic,jz4780-nemc", "simple-mfd"; 385 reg = <0x13410000 0x10000>; 386 #address-cells = <2>; 387 #size-cells = <1>; 388 ranges = <0 0 0x13410000 0x10000>, 389 <1 0 0x1b000000 0x1000000>, 390 <2 0 0x1a000000 0x1000000>, 391 <3 0 0x19000000 0x1000000>, 392 <4 0 0x18000000 0x1000000>, 393 <5 0 0x17000000 0x1000000>, 394 <6 0 0x16000000 0x1000000>; 395 396 clocks = <&cgu JZ4780_CLK_NEMC>; 397 398 status = "disabled"; 399 400 efuse: efuse@d0 { 401 reg = <0 0xd0 0x30>; 402 compatible = "ingenic,jz4780-efuse"; 403 404 clocks = <&cgu JZ4780_CLK_AHB2>; 405 406 #address-cells = <1>; 407 #size-cells = <1>; 408 409 eth0_addr: eth-mac-addr@0x22 { 410 reg = <0x22 0x6>; 411 }; 412 }; 413 }; 414 415 dma: dma@13420000 { 416 compatible = "ingenic,jz4780-dma"; 417 reg = <0x13420000 0x400>, <0x13421000 0x40>; 418 #dma-cells = <2>; 419 420 interrupt-parent = <&intc>; 421 interrupts = <10>; 422 423 clocks = <&cgu JZ4780_CLK_PDMA>; 424 }; 425 426 mmc0: mmc@13450000 { 427 compatible = "ingenic,jz4780-mmc"; 428 reg = <0x13450000 0x1000>; 429 430 interrupt-parent = <&intc>; 431 interrupts = <37>; 432 433 clocks = <&cgu JZ4780_CLK_MSC0>; 434 clock-names = "mmc"; 435 436 cap-sd-highspeed; 437 cap-mmc-highspeed; 438 cap-sdio-irq; 439 dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>, 440 <&dma JZ4780_DMA_MSC0_TX 0xffffffff>; 441 dma-names = "rx", "tx"; 442 443 status = "disabled"; 444 }; 445 446 mmc1: mmc@13460000 { 447 compatible = "ingenic,jz4780-mmc"; 448 reg = <0x13460000 0x1000>; 449 450 interrupt-parent = <&intc>; 451 interrupts = <36>; 452 453 clocks = <&cgu JZ4780_CLK_MSC1>; 454 clock-names = "mmc"; 455 456 cap-sd-highspeed; 457 cap-mmc-highspeed; 458 cap-sdio-irq; 459 dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>, 460 <&dma JZ4780_DMA_MSC1_TX 0xffffffff>; 461 dma-names = "rx", "tx"; 462 463 status = "disabled"; 464 }; 465 466 bch: bch@134d0000 { 467 compatible = "ingenic,jz4780-bch"; 468 reg = <0x134d0000 0x10000>; 469 470 clocks = <&cgu JZ4780_CLK_BCH>; 471 472 status = "disabled"; 473 }; 474}; 475