1/* 2 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. 3 * 4 * This device tree is pruned and patched by early boot code before 5 * use. Because of this, it contains a super-set of the available 6 * devices and properties. 7 */ 8 9/include/ "octeon_3xxx.dtsi" 10 11/ { 12 soc@0 { 13 smi0: mdio@1180000001800 { 14 phy0: ethernet-phy@0 { 15 compatible = "marvell,88e1118"; 16 marvell,reg-init = 17 /* Fix rx and tx clock transition timing */ 18 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ 19 /* Adjust LED drive. */ 20 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ 21 /* irq, blink-activity, blink-link */ 22 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ 23 reg = <0>; 24 }; 25 26 phy1: ethernet-phy@1 { 27 compatible = "marvell,88e1118"; 28 marvell,reg-init = 29 /* Fix rx and tx clock transition timing */ 30 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ 31 /* Adjust LED drive. */ 32 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ 33 /* irq, blink-activity, blink-link */ 34 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ 35 reg = <1>; 36 }; 37 38 phy2: ethernet-phy@2 { 39 reg = <2>; 40 compatible = "marvell,88e1149r"; 41 marvell,reg-init = <3 0x10 0 0x5777>, 42 <3 0x11 0 0x00aa>, 43 <3 0x12 0 0x4105>, 44 <3 0x13 0 0x0a60>; 45 }; 46 phy3: ethernet-phy@3 { 47 reg = <3>; 48 compatible = "marvell,88e1149r"; 49 marvell,reg-init = <3 0x10 0 0x5777>, 50 <3 0x11 0 0x00aa>, 51 <3 0x12 0 0x4105>, 52 <3 0x13 0 0x0a60>; 53 }; 54 phy4: ethernet-phy@4 { 55 reg = <4>; 56 compatible = "marvell,88e1149r"; 57 marvell,reg-init = <3 0x10 0 0x5777>, 58 <3 0x11 0 0x00aa>, 59 <3 0x12 0 0x4105>, 60 <3 0x13 0 0x0a60>; 61 }; 62 phy5: ethernet-phy@5 { 63 reg = <5>; 64 compatible = "marvell,88e1149r"; 65 marvell,reg-init = <3 0x10 0 0x5777>, 66 <3 0x11 0 0x00aa>, 67 <3 0x12 0 0x4105>, 68 <3 0x13 0 0x0a60>; 69 }; 70 71 phy6: ethernet-phy@6 { 72 reg = <6>; 73 compatible = "marvell,88e1149r"; 74 marvell,reg-init = <3 0x10 0 0x5777>, 75 <3 0x11 0 0x00aa>, 76 <3 0x12 0 0x4105>, 77 <3 0x13 0 0x0a60>; 78 }; 79 phy7: ethernet-phy@7 { 80 reg = <7>; 81 compatible = "marvell,88e1149r"; 82 marvell,reg-init = <3 0x10 0 0x5777>, 83 <3 0x11 0 0x00aa>, 84 <3 0x12 0 0x4105>, 85 <3 0x13 0 0x0a60>; 86 }; 87 phy8: ethernet-phy@8 { 88 reg = <8>; 89 compatible = "marvell,88e1149r"; 90 marvell,reg-init = <3 0x10 0 0x5777>, 91 <3 0x11 0 0x00aa>, 92 <3 0x12 0 0x4105>, 93 <3 0x13 0 0x0a60>; 94 }; 95 phy9: ethernet-phy@9 { 96 reg = <9>; 97 compatible = "marvell,88e1149r"; 98 marvell,reg-init = <3 0x10 0 0x5777>, 99 <3 0x11 0 0x00aa>, 100 <3 0x12 0 0x4105>, 101 <3 0x13 0 0x0a60>; 102 }; 103 }; 104 105 smi1: mdio@1180000001900 { 106 compatible = "cavium,octeon-3860-mdio"; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 reg = <0x11800 0x00001900 0x0 0x40>; 110 111 phy100: ethernet-phy@1 { 112 reg = <1>; 113 compatible = "marvell,88e1149r"; 114 marvell,reg-init = <3 0x10 0 0x5777>, 115 <3 0x11 0 0x00aa>, 116 <3 0x12 0 0x4105>, 117 <3 0x13 0 0x0a60>; 118 interrupt-parent = <&gpio>; 119 interrupts = <12 8>; /* Pin 12, active low */ 120 }; 121 phy101: ethernet-phy@2 { 122 reg = <2>; 123 compatible = "marvell,88e1149r"; 124 marvell,reg-init = <3 0x10 0 0x5777>, 125 <3 0x11 0 0x00aa>, 126 <3 0x12 0 0x4105>, 127 <3 0x13 0 0x0a60>; 128 interrupt-parent = <&gpio>; 129 interrupts = <12 8>; /* Pin 12, active low */ 130 }; 131 phy102: ethernet-phy@3 { 132 reg = <3>; 133 compatible = "marvell,88e1149r"; 134 marvell,reg-init = <3 0x10 0 0x5777>, 135 <3 0x11 0 0x00aa>, 136 <3 0x12 0 0x4105>, 137 <3 0x13 0 0x0a60>; 138 interrupt-parent = <&gpio>; 139 interrupts = <12 8>; /* Pin 12, active low */ 140 }; 141 phy103: ethernet-phy@4 { 142 reg = <4>; 143 compatible = "marvell,88e1149r"; 144 marvell,reg-init = <3 0x10 0 0x5777>, 145 <3 0x11 0 0x00aa>, 146 <3 0x12 0 0x4105>, 147 <3 0x13 0 0x0a60>; 148 interrupt-parent = <&gpio>; 149 interrupts = <12 8>; /* Pin 12, active low */ 150 }; 151 }; 152 153 mix0: ethernet@1070000100000 { 154 compatible = "cavium,octeon-5750-mix"; 155 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ 156 <0x11800 0xE0000000 0x0 0x300>, /* AGL */ 157 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ 158 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ 159 cell-index = <0>; 160 interrupts = <0 62>, <1 46>; 161 local-mac-address = [ 00 00 00 00 00 00 ]; 162 phy-handle = <&phy0>; 163 }; 164 165 mix1: ethernet@1070000100800 { 166 compatible = "cavium,octeon-5750-mix"; 167 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ 168 <0x11800 0xE0000800 0x0 0x300>, /* AGL */ 169 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ 170 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ 171 cell-index = <1>; 172 interrupts = <1 18>, < 1 46>; 173 local-mac-address = [ 00 00 00 00 00 00 ]; 174 phy-handle = <&phy1>; 175 }; 176 177 pip: pip@11800a0000000 { 178 interface@0 { 179 ethernet@0 { 180 phy-handle = <&phy2>; 181 cavium,alt-phy-handle = <&phy100>; 182 }; 183 ethernet@1 { 184 phy-handle = <&phy3>; 185 cavium,alt-phy-handle = <&phy101>; 186 }; 187 ethernet@2 { 188 phy-handle = <&phy4>; 189 cavium,alt-phy-handle = <&phy102>; 190 }; 191 ethernet@3 { 192 compatible = "cavium,octeon-3860-pip-port"; 193 reg = <0x3>; /* Port */ 194 local-mac-address = [ 00 00 00 00 00 00 ]; 195 phy-handle = <&phy5>; 196 cavium,alt-phy-handle = <&phy103>; 197 }; 198 ethernet@4 { 199 compatible = "cavium,octeon-3860-pip-port"; 200 reg = <0x4>; /* Port */ 201 local-mac-address = [ 00 00 00 00 00 00 ]; 202 }; 203 ethernet@5 { 204 compatible = "cavium,octeon-3860-pip-port"; 205 reg = <0x5>; /* Port */ 206 local-mac-address = [ 00 00 00 00 00 00 ]; 207 }; 208 ethernet@6 { 209 compatible = "cavium,octeon-3860-pip-port"; 210 reg = <0x6>; /* Port */ 211 local-mac-address = [ 00 00 00 00 00 00 ]; 212 }; 213 ethernet@7 { 214 compatible = "cavium,octeon-3860-pip-port"; 215 reg = <0x7>; /* Port */ 216 local-mac-address = [ 00 00 00 00 00 00 ]; 217 }; 218 ethernet@8 { 219 compatible = "cavium,octeon-3860-pip-port"; 220 reg = <0x8>; /* Port */ 221 local-mac-address = [ 00 00 00 00 00 00 ]; 222 }; 223 ethernet@9 { 224 compatible = "cavium,octeon-3860-pip-port"; 225 reg = <0x9>; /* Port */ 226 local-mac-address = [ 00 00 00 00 00 00 ]; 227 }; 228 ethernet@a { 229 compatible = "cavium,octeon-3860-pip-port"; 230 reg = <0xa>; /* Port */ 231 local-mac-address = [ 00 00 00 00 00 00 ]; 232 }; 233 ethernet@b { 234 compatible = "cavium,octeon-3860-pip-port"; 235 reg = <0xb>; /* Port */ 236 local-mac-address = [ 00 00 00 00 00 00 ]; 237 }; 238 ethernet@c { 239 compatible = "cavium,octeon-3860-pip-port"; 240 reg = <0xc>; /* Port */ 241 local-mac-address = [ 00 00 00 00 00 00 ]; 242 }; 243 ethernet@d { 244 compatible = "cavium,octeon-3860-pip-port"; 245 reg = <0xd>; /* Port */ 246 local-mac-address = [ 00 00 00 00 00 00 ]; 247 }; 248 ethernet@e { 249 compatible = "cavium,octeon-3860-pip-port"; 250 reg = <0xe>; /* Port */ 251 local-mac-address = [ 00 00 00 00 00 00 ]; 252 }; 253 ethernet@f { 254 compatible = "cavium,octeon-3860-pip-port"; 255 reg = <0xf>; /* Port */ 256 local-mac-address = [ 00 00 00 00 00 00 ]; 257 }; 258 }; 259 260 interface@1 { 261 ethernet@0 { 262 compatible = "cavium,octeon-3860-pip-port"; 263 reg = <0x0>; /* Port */ 264 local-mac-address = [ 00 00 00 00 00 00 ]; 265 phy-handle = <&phy6>; 266 }; 267 ethernet@1 { 268 compatible = "cavium,octeon-3860-pip-port"; 269 reg = <0x1>; /* Port */ 270 local-mac-address = [ 00 00 00 00 00 00 ]; 271 phy-handle = <&phy7>; 272 }; 273 ethernet@2 { 274 compatible = "cavium,octeon-3860-pip-port"; 275 reg = <0x2>; /* Port */ 276 local-mac-address = [ 00 00 00 00 00 00 ]; 277 phy-handle = <&phy8>; 278 }; 279 ethernet@3 { 280 compatible = "cavium,octeon-3860-pip-port"; 281 reg = <0x3>; /* Port */ 282 local-mac-address = [ 00 00 00 00 00 00 ]; 283 phy-handle = <&phy9>; 284 }; 285 }; 286 }; 287 288 twsi0: i2c@1180000001000 { 289 rtc@68 { 290 compatible = "dallas,ds1337"; 291 reg = <0x68>; 292 }; 293 tmp@4c { 294 compatible = "ti,tmp421"; 295 reg = <0x4c>; 296 }; 297 }; 298 299 twsi1: i2c@1180000001200 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 compatible = "cavium,octeon-3860-twsi"; 303 reg = <0x11800 0x00001200 0x0 0x200>; 304 interrupts = <0 59>; 305 clock-frequency = <100000>; 306 }; 307 308 uart1: serial@1180000000c00 { 309 compatible = "cavium,octeon-3860-uart","ns16550"; 310 reg = <0x11800 0x00000c00 0x0 0x400>; 311 clock-frequency = <0>; 312 current-speed = <115200>; 313 reg-shift = <3>; 314 interrupts = <0 35>; 315 }; 316 317 uart2: serial@1180000000400 { 318 compatible = "cavium,octeon-3860-uart","ns16550"; 319 reg = <0x11800 0x00000400 0x0 0x400>; 320 clock-frequency = <0>; 321 current-speed = <115200>; 322 reg-shift = <3>; 323 interrupts = <1 16>; 324 }; 325 326 bootbus: bootbus@1180000000000 { 327 led0: led-display@4,0 { 328 compatible = "avago,hdsp-253x"; 329 reg = <4 0x20 0x20>, <4 0 0x20>; 330 }; 331 332 cf0: compact-flash@5,0 { 333 compatible = "cavium,ebt3000-compact-flash"; 334 reg = <5 0 0x10000>, <6 0 0x10000>; 335 cavium,bus-width = <16>; 336 cavium,true-ide; 337 cavium,dma-engine-handle = <&dma0>; 338 }; 339 }; 340 341 uctl: uctl@118006f000000 { 342 compatible = "cavium,octeon-6335-uctl"; 343 reg = <0x11800 0x6f000000 0x0 0x100>; 344 ranges; /* Direct mapping */ 345 #address-cells = <2>; 346 #size-cells = <2>; 347 /* 12MHz, 24MHz and 48MHz allowed */ 348 refclk-frequency = <12000000>; 349 /* Either "crystal" or "external" */ 350 refclk-type = "crystal"; 351 352 ehci@16f0000000000 { 353 compatible = "cavium,octeon-6335-ehci","usb-ehci"; 354 reg = <0x16f00 0x00000000 0x0 0x100>; 355 interrupts = <0 56>; 356 big-endian-regs; 357 }; 358 ohci@16f0000000400 { 359 compatible = "cavium,octeon-6335-ohci","usb-ohci"; 360 reg = <0x16f00 0x00000400 0x0 0x100>; 361 interrupts = <0 56>; 362 big-endian-regs; 363 }; 364 }; 365 366 usbn: usbn@1180068000000 { 367 /* 12MHz, 24MHz and 48MHz allowed */ 368 refclk-frequency = <12000000>; 369 /* Either "crystal" or "external" */ 370 refclk-type = "crystal"; 371 }; 372 }; 373 374 aliases { 375 mix0 = &mix0; 376 mix1 = &mix1; 377 pip = &pip; 378 smi0 = &smi0; 379 smi1 = &smi1; 380 twsi0 = &twsi0; 381 twsi1 = &twsi1; 382 uart0 = &uart0; 383 uart1 = &uart1; 384 uart2 = &uart2; 385 flash0 = &flash0; 386 cf0 = &cf0; 387 uctl = &uctl; 388 usbn = &usbn; 389 led0 = &led0; 390 }; 391 392 dsr1000n-leds { 393 compatible = "gpio-leds"; 394 usb1 { 395 label = "usb1"; 396 gpios = <&gpio 9 1>; /* Active low */ 397 }; 398 usb2 { 399 label = "usb2"; 400 gpios = <&gpio 10 1>; /* Active low */ 401 }; 402 }; 403 }; 404