1/ { 2 #address-cells = <1>; 3 #size-cells = <1>; 4 compatible = "brcm,bcm7420"; 5 6 cpus { 7 #address-cells = <1>; 8 #size-cells = <0>; 9 10 mips-hpt-frequency = <93750000>; 11 12 cpu@0 { 13 compatible = "brcm,bmips5000"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 18 cpu@1 { 19 compatible = "brcm,bmips5000"; 20 device_type = "cpu"; 21 reg = <1>; 22 }; 23 }; 24 25 aliases { 26 uart0 = &uart0; 27 }; 28 29 cpu_intc: interrupt-controller { 30 #address-cells = <0>; 31 compatible = "mti,cpu-interrupt-controller"; 32 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 }; 36 37 clocks { 38 uart_clk: uart_clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <81000000>; 42 }; 43 44 upg_clk: upg_clk { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <27000000>; 48 }; 49 }; 50 51 rdb { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 compatible = "simple-bus"; 56 ranges = <0 0x10000000 0x01000000>; 57 58 periph_intc: interrupt-controller@441400 { 59 compatible = "brcm,bcm7038-l1-intc"; 60 reg = <0x441400 0x30>, <0x441600 0x30>; 61 62 interrupt-controller; 63 #interrupt-cells = <1>; 64 65 interrupt-parent = <&cpu_intc>; 66 interrupts = <2>, <3>; 67 }; 68 69 sun_l2_intc: interrupt-controller@401800 { 70 compatible = "brcm,l2-intc"; 71 reg = <0x401800 0x30>; 72 interrupt-controller; 73 #interrupt-cells = <1>; 74 interrupt-parent = <&periph_intc>; 75 interrupts = <23>; 76 }; 77 78 gisb-arb@400000 { 79 compatible = "brcm,bcm7400-gisb-arb"; 80 reg = <0x400000 0xdc>; 81 native-endian; 82 interrupt-parent = <&sun_l2_intc>; 83 interrupts = <0>, <2>; 84 brcm,gisb-arb-master-mask = <0x3ff>; 85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0", 86 "pcie_0", "bsp_0", "rdc_0", 87 "rptd_0", "avd_0", "avd_1", 88 "jtag_0"; 89 }; 90 91 upg_irq0_intc: interrupt-controller@406780 { 92 compatible = "brcm,bcm7120-l2-intc"; 93 reg = <0x406780 0x8>; 94 95 brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>; 96 brcm,int-fwd-mask = <0x70000>; 97 98 interrupt-controller; 99 #interrupt-cells = <1>; 100 101 interrupt-parent = <&periph_intc>; 102 interrupts = <18>, <19>, <20>; 103 interrupt-names = "upg_main", "upg_bsc", "upg_spi"; 104 }; 105 106 sun_top_ctrl: syscon@404000 { 107 compatible = "brcm,bcm7420-sun-top-ctrl", "syscon"; 108 reg = <0x404000 0x60c>; 109 native-endian; 110 }; 111 112 reboot { 113 compatible = "brcm,bcm7038-reboot"; 114 syscon = <&sun_top_ctrl 0x8 0x14>; 115 }; 116 117 uart0: serial@406b00 { 118 compatible = "ns16550a"; 119 reg = <0x406b00 0x20>; 120 reg-io-width = <0x4>; 121 reg-shift = <0x2>; 122 interrupt-parent = <&periph_intc>; 123 interrupts = <21>; 124 clocks = <&uart_clk>; 125 status = "disabled"; 126 }; 127 128 uart1: serial@406b40 { 129 compatible = "ns16550a"; 130 reg = <0x406b40 0x20>; 131 reg-io-width = <0x4>; 132 reg-shift = <0x2>; 133 interrupt-parent = <&periph_intc>; 134 interrupts = <64>; 135 clocks = <&uart_clk>; 136 status = "disabled"; 137 }; 138 139 uart2: serial@406b80 { 140 compatible = "ns16550a"; 141 reg = <0x406b80 0x20>; 142 reg-io-width = <0x4>; 143 reg-shift = <0x2>; 144 interrupt-parent = <&periph_intc>; 145 interrupts = <65>; 146 clocks = <&uart_clk>; 147 status = "disabled"; 148 }; 149 150 bsca: i2c@406200 { 151 clock-frequency = <390000>; 152 compatible = "brcm,brcmstb-i2c"; 153 interrupt-parent = <&upg_irq0_intc>; 154 reg = <0x406200 0x58>; 155 interrupts = <24>; 156 interrupt-names = "upg_bsca"; 157 status = "disabled"; 158 }; 159 160 bscb: i2c@406280 { 161 clock-frequency = <390000>; 162 compatible = "brcm,brcmstb-i2c"; 163 interrupt-parent = <&upg_irq0_intc>; 164 reg = <0x406280 0x58>; 165 interrupts = <25>; 166 interrupt-names = "upg_bscb"; 167 status = "disabled"; 168 }; 169 170 bscc: i2c@406300 { 171 clock-frequency = <390000>; 172 compatible = "brcm,brcmstb-i2c"; 173 interrupt-parent = <&upg_irq0_intc>; 174 reg = <0x406300 0x58>; 175 interrupts = <26>; 176 interrupt-names = "upg_bscc"; 177 status = "disabled"; 178 }; 179 180 bscd: i2c@406380 { 181 clock-frequency = <390000>; 182 compatible = "brcm,brcmstb-i2c"; 183 interrupt-parent = <&upg_irq0_intc>; 184 reg = <0x406380 0x58>; 185 interrupts = <27>; 186 interrupt-names = "upg_bscd"; 187 status = "disabled"; 188 }; 189 190 bsce: i2c@406800 { 191 clock-frequency = <390000>; 192 compatible = "brcm,brcmstb-i2c"; 193 interrupt-parent = <&upg_irq0_intc>; 194 reg = <0x406800 0x58>; 195 interrupts = <28>; 196 interrupt-names = "upg_bsce"; 197 status = "disabled"; 198 }; 199 200 pwma: pwm@406580 { 201 compatible = "brcm,bcm7038-pwm"; 202 reg = <0x406580 0x28>; 203 #pwm-cells = <2>; 204 clocks = <&upg_clk>; 205 status = "disabled"; 206 }; 207 208 pwmb: pwm@406880 { 209 compatible = "brcm,bcm7038-pwm"; 210 reg = <0x406880 0x28>; 211 #pwm-cells = <2>; 212 clocks = <&upg_clk>; 213 status = "disabled"; 214 }; 215 216 upg_gio: gpio@406700 { 217 compatible = "brcm,brcmstb-gpio"; 218 reg = <0x406700 0x80>; 219 #gpio-cells = <2>; 220 #interrupt-cells = <2>; 221 gpio-controller; 222 interrupt-controller; 223 interrupt-parent = <&upg_irq0_intc>; 224 interrupts = <6>; 225 brcm,gpio-bank-widths = <32 32 32 27>; 226 }; 227 228 enet0: ethernet@468000 { 229 phy-mode = "internal"; 230 phy-handle = <&phy1>; 231 mac-address = [ 00 10 18 36 23 1a ]; 232 compatible = "brcm,genet-v1"; 233 #address-cells = <0x1>; 234 #size-cells = <0x1>; 235 reg = <0x468000 0x3c8c>; 236 interrupts = <69>, <79>; 237 interrupt-parent = <&periph_intc>; 238 status = "disabled"; 239 240 mdio@e14 { 241 compatible = "brcm,genet-mdio-v1"; 242 #address-cells = <0x1>; 243 #size-cells = <0x0>; 244 reg = <0xe14 0x8>; 245 246 phy1: ethernet-phy@1 { 247 max-speed = <100>; 248 reg = <0x1>; 249 compatible = "brcm,65nm-ephy", 250 "ethernet-phy-ieee802.3-c22"; 251 }; 252 }; 253 }; 254 255 ehci0: usb@488300 { 256 compatible = "brcm,bcm7420-ehci", "generic-ehci"; 257 reg = <0x488300 0x100>; 258 interrupt-parent = <&periph_intc>; 259 interrupts = <60>; 260 status = "disabled"; 261 }; 262 263 ohci0: usb@488400 { 264 compatible = "brcm,bcm7420-ohci", "generic-ohci"; 265 reg = <0x488400 0x100>; 266 native-endian; 267 no-big-frame-no; 268 interrupt-parent = <&periph_intc>; 269 interrupts = <61>; 270 status = "disabled"; 271 }; 272 273 ehci1: usb@488500 { 274 compatible = "brcm,bcm7420-ehci", "generic-ehci"; 275 reg = <0x488500 0x100>; 276 interrupt-parent = <&periph_intc>; 277 interrupts = <55>; 278 status = "disabled"; 279 }; 280 281 ohci1: usb@488600 { 282 compatible = "brcm,bcm7420-ohci", "generic-ohci"; 283 reg = <0x488600 0x100>; 284 native-endian; 285 no-big-frame-no; 286 interrupt-parent = <&periph_intc>; 287 interrupts = <62>; 288 status = "disabled"; 289 }; 290 291 spi_l2_intc: interrupt-controller@411d00 { 292 compatible = "brcm,l2-intc"; 293 reg = <0x411d00 0x30>; 294 interrupt-controller; 295 #interrupt-cells = <1>; 296 interrupt-parent = <&periph_intc>; 297 interrupts = <78>; 298 }; 299 300 qspi: spi@443000 { 301 #address-cells = <0x1>; 302 #size-cells = <0x0>; 303 compatible = "brcm,spi-bcm-qspi", 304 "brcm,spi-brcmstb-qspi"; 305 clocks = <&upg_clk>; 306 reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>; 307 reg-names = "cs_reg", "hif_mspi", "bspi"; 308 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 309 interrupt-parent = <&spi_l2_intc>; 310 interrupt-names = "spi_lr_fullness_reached", 311 "spi_lr_session_aborted", 312 "spi_lr_impatient", 313 "spi_lr_session_done", 314 "spi_lr_overread", 315 "mspi_done", 316 "mspi_halted"; 317 status = "disabled"; 318 }; 319 320 mspi: spi@406400 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 compatible = "brcm,spi-bcm-qspi", 324 "brcm,spi-brcmstb-mspi"; 325 clocks = <&upg_clk>; 326 reg = <0x406400 0x180>; 327 reg-names = "mspi"; 328 interrupts = <0x14>; 329 interrupt-parent = <&upg_irq0_intc>; 330 interrupt-names = "mspi_done"; 331 status = "disabled"; 332 }; 333 }; 334}; 335