1/ { 2 #address-cells = <1>; 3 #size-cells = <1>; 4 compatible = "brcm,bcm7362"; 5 6 cpus { 7 #address-cells = <1>; 8 #size-cells = <0>; 9 10 mips-hpt-frequency = <375000000>; 11 12 cpu@0 { 13 compatible = "brcm,bmips4380"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 18 cpu@1 { 19 compatible = "brcm,bmips4380"; 20 device_type = "cpu"; 21 reg = <1>; 22 }; 23 }; 24 25 aliases { 26 uart0 = &uart0; 27 }; 28 29 cpu_intc: interrupt-controller { 30 #address-cells = <0>; 31 compatible = "mti,cpu-interrupt-controller"; 32 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 }; 36 37 clocks { 38 uart_clk: uart_clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <81000000>; 42 }; 43 44 upg_clk: upg_clk { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <27000000>; 48 }; 49 }; 50 51 rdb { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 compatible = "simple-bus"; 56 ranges = <0 0x10000000 0x01000000>; 57 58 periph_intc: interrupt-controller@411400 { 59 compatible = "brcm,bcm7038-l1-intc"; 60 reg = <0x411400 0x30>, <0x411600 0x30>; 61 62 interrupt-controller; 63 #interrupt-cells = <1>; 64 65 interrupt-parent = <&cpu_intc>; 66 interrupts = <2>, <3>; 67 }; 68 69 sun_l2_intc: interrupt-controller@403000 { 70 compatible = "brcm,l2-intc"; 71 reg = <0x403000 0x30>; 72 interrupt-controller; 73 #interrupt-cells = <1>; 74 interrupt-parent = <&periph_intc>; 75 interrupts = <48>; 76 }; 77 78 gisb-arb@400000 { 79 compatible = "brcm,bcm7400-gisb-arb"; 80 reg = <0x400000 0xdc>; 81 native-endian; 82 interrupt-parent = <&sun_l2_intc>; 83 interrupts = <0>, <2>; 84 brcm,gisb-arb-master-mask = <0x2f3>; 85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 86 "rdc_0", "raaga_0", 87 "avd_0", "jtag_0"; 88 }; 89 90 upg_irq0_intc: interrupt-controller@406600 { 91 compatible = "brcm,bcm7120-l2-intc"; 92 reg = <0x406600 0x8>; 93 94 brcm,int-map-mask = <0x44>, <0x7000000>; 95 brcm,int-fwd-mask = <0x70000>; 96 97 interrupt-controller; 98 #interrupt-cells = <1>; 99 100 interrupt-parent = <&periph_intc>; 101 interrupts = <56>, <54>; 102 interrupt-names = "upg_main", "upg_bsc"; 103 }; 104 105 upg_aon_irq0_intc: interrupt-controller@408b80 { 106 compatible = "brcm,bcm7120-l2-intc"; 107 reg = <0x408b80 0x8>; 108 109 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; 110 brcm,int-fwd-mask = <0>; 111 brcm,irq-can-wake; 112 113 interrupt-controller; 114 #interrupt-cells = <1>; 115 116 interrupt-parent = <&periph_intc>; 117 interrupts = <57>, <55>, <59>; 118 interrupt-names = "upg_main_aon", "upg_bsc_aon", 119 "upg_spi"; 120 }; 121 122 sun_top_ctrl: syscon@404000 { 123 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon"; 124 reg = <0x404000 0x51c>; 125 native-endian; 126 }; 127 128 reboot { 129 compatible = "brcm,brcmstb-reboot"; 130 syscon = <&sun_top_ctrl 0x304 0x308>; 131 }; 132 133 uart0: serial@406800 { 134 compatible = "ns16550a"; 135 reg = <0x406800 0x20>; 136 reg-io-width = <0x4>; 137 reg-shift = <0x2>; 138 native-endian; 139 interrupt-parent = <&periph_intc>; 140 interrupts = <61>; 141 clocks = <&uart_clk>; 142 status = "disabled"; 143 }; 144 145 uart1: serial@406840 { 146 compatible = "ns16550a"; 147 reg = <0x406840 0x20>; 148 reg-io-width = <0x4>; 149 reg-shift = <0x2>; 150 native-endian; 151 interrupt-parent = <&periph_intc>; 152 interrupts = <62>; 153 clocks = <&uart_clk>; 154 status = "disabled"; 155 }; 156 157 uart2: serial@406880 { 158 compatible = "ns16550a"; 159 reg = <0x406880 0x20>; 160 reg-io-width = <0x4>; 161 reg-shift = <0x2>; 162 native-endian; 163 interrupt-parent = <&periph_intc>; 164 interrupts = <63>; 165 clocks = <&uart_clk>; 166 status = "disabled"; 167 }; 168 169 bsca: i2c@406200 { 170 clock-frequency = <390000>; 171 compatible = "brcm,brcmstb-i2c"; 172 interrupt-parent = <&upg_irq0_intc>; 173 reg = <0x406200 0x58>; 174 interrupts = <24>; 175 interrupt-names = "upg_bsca"; 176 status = "disabled"; 177 }; 178 179 bscb: i2c@406280 { 180 clock-frequency = <390000>; 181 compatible = "brcm,brcmstb-i2c"; 182 interrupt-parent = <&upg_irq0_intc>; 183 reg = <0x406280 0x58>; 184 interrupts = <25>; 185 interrupt-names = "upg_bscb"; 186 status = "disabled"; 187 }; 188 189 bscd: i2c@408980 { 190 clock-frequency = <390000>; 191 compatible = "brcm,brcmstb-i2c"; 192 interrupt-parent = <&upg_aon_irq0_intc>; 193 reg = <0x408980 0x58>; 194 interrupts = <27>; 195 interrupt-names = "upg_bscd"; 196 status = "disabled"; 197 }; 198 199 pwma: pwm@406400 { 200 compatible = "brcm,bcm7038-pwm"; 201 reg = <0x406400 0x28>; 202 #pwm-cells = <2>; 203 clocks = <&upg_clk>; 204 status = "disabled"; 205 }; 206 207 aon_pm_l2_intc: interrupt-controller@408440 { 208 compatible = "brcm,l2-intc"; 209 reg = <0x408440 0x30>; 210 interrupt-controller; 211 #interrupt-cells = <1>; 212 interrupt-parent = <&periph_intc>; 213 interrupts = <50>; 214 brcm,irq-can-wake; 215 }; 216 217 upg_gio: gpio@406500 { 218 compatible = "brcm,brcmstb-gpio"; 219 reg = <0x406500 0xa0>; 220 #gpio-cells = <2>; 221 #interrupt-cells = <2>; 222 gpio-controller; 223 interrupt-controller; 224 interrupt-parent = <&upg_irq0_intc>; 225 interrupts = <6>; 226 brcm,gpio-bank-widths = <32 32 32 29 4>; 227 }; 228 229 upg_gio_aon: gpio@408c00 { 230 compatible = "brcm,brcmstb-gpio"; 231 reg = <0x408c00 0x60>; 232 #gpio-cells = <2>; 233 #interrupt-cells = <2>; 234 gpio-controller; 235 interrupt-controller; 236 interrupt-parent = <&upg_aon_irq0_intc>; 237 interrupts = <6>; 238 interrupts-extended = <&upg_aon_irq0_intc 6>, 239 <&aon_pm_l2_intc 5>; 240 wakeup-source; 241 brcm,gpio-bank-widths = <21 32 2>; 242 }; 243 244 enet0: ethernet@430000 { 245 phy-mode = "internal"; 246 phy-handle = <&phy1>; 247 mac-address = [ 00 10 18 36 23 1a ]; 248 compatible = "brcm,genet-v2"; 249 #address-cells = <0x1>; 250 #size-cells = <0x1>; 251 reg = <0x430000 0x4c8c>; 252 interrupts = <24>, <25>; 253 interrupt-parent = <&periph_intc>; 254 status = "disabled"; 255 256 mdio@e14 { 257 compatible = "brcm,genet-mdio-v2"; 258 #address-cells = <0x1>; 259 #size-cells = <0x0>; 260 reg = <0xe14 0x8>; 261 262 phy1: ethernet-phy@1 { 263 max-speed = <100>; 264 reg = <0x1>; 265 compatible = "brcm,40nm-ephy", 266 "ethernet-phy-ieee802.3-c22"; 267 }; 268 }; 269 }; 270 271 ehci0: usb@480300 { 272 compatible = "brcm,bcm7362-ehci", "generic-ehci"; 273 reg = <0x480300 0x100>; 274 native-endian; 275 interrupt-parent = <&periph_intc>; 276 interrupts = <65>; 277 status = "disabled"; 278 }; 279 280 ohci0: usb@480400 { 281 compatible = "brcm,bcm7362-ohci", "generic-ohci"; 282 reg = <0x480400 0x100>; 283 native-endian; 284 no-big-frame-no; 285 interrupt-parent = <&periph_intc>; 286 interrupts = <66>; 287 status = "disabled"; 288 }; 289 290 hif_l2_intc: interrupt-controller@411000 { 291 compatible = "brcm,l2-intc"; 292 reg = <0x411000 0x30>; 293 interrupt-controller; 294 #interrupt-cells = <1>; 295 interrupt-parent = <&periph_intc>; 296 interrupts = <30>; 297 }; 298 299 nand: nand@412800 { 300 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 reg-names = "nand"; 304 reg = <0x412800 0x400>; 305 interrupt-parent = <&hif_l2_intc>; 306 interrupts = <24>; 307 status = "disabled"; 308 }; 309 310 sata: sata@181000 { 311 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; 312 reg-names = "ahci", "top-ctrl"; 313 reg = <0x181000 0xa9c>, <0x180020 0x1c>; 314 interrupt-parent = <&periph_intc>; 315 interrupts = <86>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 status = "disabled"; 319 320 sata0: sata-port@0 { 321 reg = <0>; 322 phys = <&sata_phy0>; 323 }; 324 325 sata1: sata-port@1 { 326 reg = <1>; 327 phys = <&sata_phy1>; 328 }; 329 }; 330 331 sata_phy: sata-phy@180100 { 332 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; 333 reg = <0x180100 0x0eff>; 334 reg-names = "phy"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 status = "disabled"; 338 339 sata_phy0: sata-phy@0 { 340 reg = <0>; 341 #phy-cells = <0>; 342 }; 343 344 sata_phy1: sata-phy@1 { 345 reg = <1>; 346 #phy-cells = <0>; 347 }; 348 }; 349 350 sdhci0: sdhci@410000 { 351 compatible = "brcm,bcm7425-sdhci"; 352 reg = <0x410000 0x100>; 353 interrupt-parent = <&periph_intc>; 354 interrupts = <82>; 355 status = "disabled"; 356 }; 357 358 spi_l2_intc: interrupt-controller@411d00 { 359 compatible = "brcm,l2-intc"; 360 reg = <0x411d00 0x30>; 361 interrupt-controller; 362 #interrupt-cells = <1>; 363 interrupt-parent = <&periph_intc>; 364 interrupts = <31>; 365 }; 366 367 qspi: spi@413000 { 368 #address-cells = <0x1>; 369 #size-cells = <0x0>; 370 compatible = "brcm,spi-bcm-qspi", 371 "brcm,spi-brcmstb-qspi"; 372 clocks = <&upg_clk>; 373 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; 374 reg-names = "cs_reg", "hif_mspi", "bspi"; 375 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 376 interrupt-parent = <&spi_l2_intc>; 377 interrupt-names = "spi_lr_fullness_reached", 378 "spi_lr_session_aborted", 379 "spi_lr_impatient", 380 "spi_lr_session_done", 381 "spi_lr_overread", 382 "mspi_done", 383 "mspi_halted"; 384 status = "disabled"; 385 }; 386 387 mspi: spi@408a00 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 compatible = "brcm,spi-bcm-qspi", 391 "brcm,spi-brcmstb-mspi"; 392 clocks = <&upg_clk>; 393 reg = <0x408a00 0x180>; 394 reg-names = "mspi"; 395 interrupts = <0x14>; 396 interrupt-parent = <&upg_aon_irq0_intc>; 397 interrupt-names = "mspi_done"; 398 status = "disabled"; 399 }; 400 }; 401}; 402