1// SPDX-License-Identifier: GPL-2.0 2/ { 3 #address-cells = <1>; 4 #size-cells = <1>; 5 compatible = "brcm,bcm7360"; 6 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 11 mips-hpt-frequency = <375000000>; 12 13 cpu@0 { 14 compatible = "brcm,bmips3300"; 15 device_type = "cpu"; 16 reg = <0>; 17 }; 18 }; 19 20 aliases { 21 uart0 = &uart0; 22 }; 23 24 cpu_intc: interrupt-controller { 25 #address-cells = <0>; 26 compatible = "mti,cpu-interrupt-controller"; 27 28 interrupt-controller; 29 #interrupt-cells = <1>; 30 }; 31 32 clocks { 33 uart_clk: uart_clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <81000000>; 37 }; 38 39 upg_clk: upg_clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <27000000>; 43 }; 44 }; 45 46 rdb { 47 #address-cells = <1>; 48 #size-cells = <1>; 49 50 compatible = "simple-bus"; 51 ranges = <0 0x10000000 0x01000000>; 52 53 periph_intc: interrupt-controller@411400 { 54 compatible = "brcm,bcm7038-l1-intc"; 55 reg = <0x411400 0x30>; 56 57 interrupt-controller; 58 #interrupt-cells = <1>; 59 60 interrupt-parent = <&cpu_intc>; 61 interrupts = <2>; 62 }; 63 64 sun_l2_intc: interrupt-controller@403000 { 65 compatible = "brcm,l2-intc"; 66 reg = <0x403000 0x30>; 67 interrupt-controller; 68 #interrupt-cells = <1>; 69 interrupt-parent = <&periph_intc>; 70 interrupts = <48>; 71 }; 72 73 gisb-arb@400000 { 74 compatible = "brcm,bcm7400-gisb-arb"; 75 reg = <0x400000 0xdc>; 76 native-endian; 77 interrupt-parent = <&sun_l2_intc>; 78 interrupts = <0>, <2>; 79 brcm,gisb-arb-master-mask = <0x2f3>; 80 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 81 "rdc_0", "raaga_0", 82 "avd_0", "jtag_0"; 83 }; 84 85 upg_irq0_intc: interrupt-controller@406600 { 86 compatible = "brcm,bcm7120-l2-intc"; 87 reg = <0x406600 0x8>; 88 89 brcm,int-map-mask = <0x44>, <0x7000000>; 90 brcm,int-fwd-mask = <0x70000>; 91 92 interrupt-controller; 93 #interrupt-cells = <1>; 94 95 interrupt-parent = <&periph_intc>; 96 interrupts = <56>, <54>; 97 interrupt-names = "upg_main", "upg_bsc"; 98 }; 99 100 upg_aon_irq0_intc: interrupt-controller@408b80 { 101 compatible = "brcm,bcm7120-l2-intc"; 102 reg = <0x408b80 0x8>; 103 104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; 105 brcm,int-fwd-mask = <0>; 106 brcm,irq-can-wake; 107 108 interrupt-controller; 109 #interrupt-cells = <1>; 110 111 interrupt-parent = <&periph_intc>; 112 interrupts = <57>, <55>, <59>; 113 interrupt-names = "upg_main_aon", "upg_bsc_aon", 114 "upg_spi"; 115 }; 116 117 sun_top_ctrl: syscon@404000 { 118 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon"; 119 reg = <0x404000 0x51c>; 120 native-endian; 121 }; 122 123 reboot { 124 compatible = "brcm,brcmstb-reboot"; 125 syscon = <&sun_top_ctrl 0x304 0x308>; 126 }; 127 128 uart0: serial@406800 { 129 compatible = "ns16550a"; 130 reg = <0x406800 0x20>; 131 reg-io-width = <0x4>; 132 reg-shift = <0x2>; 133 native-endian; 134 interrupt-parent = <&periph_intc>; 135 interrupts = <61>; 136 clocks = <&uart_clk>; 137 status = "disabled"; 138 }; 139 140 uart1: serial@406840 { 141 compatible = "ns16550a"; 142 reg = <0x406840 0x20>; 143 reg-io-width = <0x4>; 144 reg-shift = <0x2>; 145 native-endian; 146 interrupt-parent = <&periph_intc>; 147 interrupts = <62>; 148 clocks = <&uart_clk>; 149 status = "disabled"; 150 }; 151 152 uart2: serial@406880 { 153 compatible = "ns16550a"; 154 reg = <0x406880 0x20>; 155 reg-io-width = <0x4>; 156 reg-shift = <0x2>; 157 native-endian; 158 interrupt-parent = <&periph_intc>; 159 interrupts = <63>; 160 clocks = <&uart_clk>; 161 status = "disabled"; 162 }; 163 164 bsca: i2c@406200 { 165 clock-frequency = <390000>; 166 compatible = "brcm,brcmstb-i2c"; 167 interrupt-parent = <&upg_irq0_intc>; 168 reg = <0x406200 0x58>; 169 interrupts = <24>; 170 interrupt-names = "upg_bsca"; 171 status = "disabled"; 172 }; 173 174 bscb: i2c@406280 { 175 clock-frequency = <390000>; 176 compatible = "brcm,brcmstb-i2c"; 177 interrupt-parent = <&upg_irq0_intc>; 178 reg = <0x406280 0x58>; 179 interrupts = <25>; 180 interrupt-names = "upg_bscb"; 181 status = "disabled"; 182 }; 183 184 bscc: i2c@406300 { 185 clock-frequency = <390000>; 186 compatible = "brcm,brcmstb-i2c"; 187 interrupt-parent = <&upg_irq0_intc>; 188 reg = <0x406300 0x58>; 189 interrupts = <26>; 190 interrupt-names = "upg_bscc"; 191 status = "disabled"; 192 }; 193 194 bscd: i2c@408980 { 195 clock-frequency = <390000>; 196 compatible = "brcm,brcmstb-i2c"; 197 interrupt-parent = <&upg_aon_irq0_intc>; 198 reg = <0x408980 0x58>; 199 interrupts = <27>; 200 interrupt-names = "upg_bscd"; 201 status = "disabled"; 202 }; 203 204 pwma: pwm@406400 { 205 compatible = "brcm,bcm7038-pwm"; 206 reg = <0x406400 0x28>; 207 #pwm-cells = <2>; 208 clocks = <&upg_clk>; 209 status = "disabled"; 210 }; 211 212 aon_pm_l2_intc: interrupt-controller@408440 { 213 compatible = "brcm,l2-intc"; 214 reg = <0x408440 0x30>; 215 interrupt-controller; 216 #interrupt-cells = <1>; 217 interrupt-parent = <&periph_intc>; 218 interrupts = <50>; 219 brcm,irq-can-wake; 220 }; 221 222 aon_ctrl: syscon@408000 { 223 compatible = "brcm,brcmstb-aon-ctrl"; 224 reg = <0x408000 0x100>, <0x408200 0x200>; 225 reg-names = "aon-ctrl", "aon-sram"; 226 }; 227 228 timers: timer@406680 { 229 compatible = "brcm,brcmstb-timers"; 230 reg = <0x406680 0x40>; 231 }; 232 233 upg_gio: gpio@406500 { 234 compatible = "brcm,brcmstb-gpio"; 235 reg = <0x406500 0xa0>; 236 #gpio-cells = <2>; 237 #interrupt-cells = <2>; 238 gpio-controller; 239 interrupt-controller; 240 interrupt-parent = <&upg_irq0_intc>; 241 interrupts = <6>; 242 brcm,gpio-bank-widths = <32 32 32 29 4>; 243 }; 244 245 upg_gio_aon: gpio@408c00 { 246 compatible = "brcm,brcmstb-gpio"; 247 reg = <0x408c00 0x60>; 248 #gpio-cells = <2>; 249 #interrupt-cells = <2>; 250 gpio-controller; 251 interrupt-controller; 252 interrupt-parent = <&upg_aon_irq0_intc>; 253 interrupts = <6>; 254 interrupts-extended = <&upg_aon_irq0_intc 6>, 255 <&aon_pm_l2_intc 5>; 256 wakeup-source; 257 brcm,gpio-bank-widths = <21 32 2>; 258 }; 259 260 enet0: ethernet@430000 { 261 phy-mode = "internal"; 262 phy-handle = <&phy1>; 263 mac-address = [ 00 10 18 36 23 1a ]; 264 compatible = "brcm,genet-v2"; 265 #address-cells = <0x1>; 266 #size-cells = <0x1>; 267 reg = <0x430000 0x4c8c>; 268 interrupts = <24>, <25>; 269 interrupt-parent = <&periph_intc>; 270 status = "disabled"; 271 272 mdio@e14 { 273 compatible = "brcm,genet-mdio-v2"; 274 #address-cells = <0x1>; 275 #size-cells = <0x0>; 276 reg = <0xe14 0x8>; 277 278 phy1: ethernet-phy@1 { 279 max-speed = <100>; 280 reg = <0x1>; 281 compatible = "brcm,40nm-ephy", 282 "ethernet-phy-ieee802.3-c22"; 283 }; 284 }; 285 }; 286 287 ehci0: usb@480300 { 288 compatible = "brcm,bcm7360-ehci", "generic-ehci"; 289 reg = <0x480300 0x100>; 290 native-endian; 291 interrupt-parent = <&periph_intc>; 292 interrupts = <65>; 293 status = "disabled"; 294 }; 295 296 ohci0: usb@480400 { 297 compatible = "brcm,bcm7360-ohci", "generic-ohci"; 298 reg = <0x480400 0x100>; 299 native-endian; 300 no-big-frame-no; 301 interrupt-parent = <&periph_intc>; 302 interrupts = <66>; 303 status = "disabled"; 304 }; 305 306 hif_l2_intc: interrupt-controller@411000 { 307 compatible = "brcm,l2-intc"; 308 reg = <0x411000 0x30>; 309 interrupt-controller; 310 #interrupt-cells = <1>; 311 interrupt-parent = <&periph_intc>; 312 interrupts = <30>; 313 }; 314 315 nand: nand@412800 { 316 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg-names = "nand"; 320 reg = <0x412800 0x400>; 321 interrupt-parent = <&hif_l2_intc>; 322 interrupts = <24>; 323 status = "disabled"; 324 }; 325 326 sata: sata@181000 { 327 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; 328 reg-names = "ahci", "top-ctrl"; 329 reg = <0x181000 0xa9c>, <0x180020 0x1c>; 330 interrupt-parent = <&periph_intc>; 331 interrupts = <86>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 status = "disabled"; 335 336 sata0: sata-port@0 { 337 reg = <0>; 338 phys = <&sata_phy0>; 339 }; 340 341 sata1: sata-port@1 { 342 reg = <1>; 343 phys = <&sata_phy1>; 344 }; 345 }; 346 347 sata_phy: sata-phy@180100 { 348 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; 349 reg = <0x180100 0x0eff>; 350 reg-names = "phy"; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 status = "disabled"; 354 355 sata_phy0: sata-phy@0 { 356 reg = <0>; 357 #phy-cells = <0>; 358 }; 359 360 sata_phy1: sata-phy@1 { 361 reg = <1>; 362 #phy-cells = <0>; 363 }; 364 }; 365 366 sdhci0: sdhci@410000 { 367 compatible = "brcm,bcm7425-sdhci"; 368 reg = <0x410000 0x100>; 369 interrupt-parent = <&periph_intc>; 370 interrupts = <82>; 371 status = "disabled"; 372 }; 373 374 spi_l2_intc: interrupt-controller@411d00 { 375 compatible = "brcm,l2-intc"; 376 reg = <0x411d00 0x30>; 377 interrupt-controller; 378 #interrupt-cells = <1>; 379 interrupt-parent = <&periph_intc>; 380 interrupts = <31>; 381 }; 382 383 qspi: spi@413000 { 384 #address-cells = <0x1>; 385 #size-cells = <0x0>; 386 compatible = "brcm,spi-bcm-qspi", 387 "brcm,spi-brcmstb-qspi"; 388 clocks = <&upg_clk>; 389 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; 390 reg-names = "cs_reg", "hif_mspi", "bspi"; 391 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 392 interrupt-parent = <&spi_l2_intc>; 393 interrupt-names = "spi_lr_fullness_reached", 394 "spi_lr_session_aborted", 395 "spi_lr_impatient", 396 "spi_lr_session_done", 397 "spi_lr_overread", 398 "mspi_done", 399 "mspi_halted"; 400 status = "disabled"; 401 }; 402 403 mspi: spi@408a00 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 compatible = "brcm,spi-bcm-qspi", 407 "brcm,spi-brcmstb-mspi"; 408 clocks = <&upg_clk>; 409 reg = <0x408a00 0x180>; 410 reg-names = "mspi"; 411 interrupts = <0x14>; 412 interrupt-parent = <&upg_aon_irq0_intc>; 413 interrupt-names = "mspi_done"; 414 status = "disabled"; 415 }; 416 417 waketimer: waketimer@408e80 { 418 compatible = "brcm,brcmstb-waketimer"; 419 reg = <0x408e80 0x14>; 420 interrupts = <0x3>; 421 interrupt-parent = <&aon_pm_l2_intc>; 422 interrupt-names = "timer"; 423 clocks = <&upg_clk>; 424 status = "disabled"; 425 }; 426 }; 427 428 memory_controllers { 429 compatible = "simple-bus"; 430 ranges = <0x0 0x103b0000 0xa000>; 431 #address-cells = <1>; 432 #size-cells = <1>; 433 434 memory-controller@0 { 435 compatible = "brcm,brcmstb-memc", "simple-bus"; 436 ranges = <0x0 0x0 0xa000>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 440 memc-arb@1000 { 441 compatible = "brcm,brcmstb-memc-arb"; 442 reg = <0x1000 0x248>; 443 }; 444 445 memc-ddr@2000 { 446 compatible = "brcm,brcmstb-memc-ddr"; 447 reg = <0x2000 0x300>; 448 }; 449 450 ddr-phy@6000 { 451 compatible = "brcm,brcmstb-ddr-phy"; 452 reg = <0x6000 0xc8>; 453 }; 454 455 shimphy@8000 { 456 compatible = "brcm,brcmstb-ddr-shimphy"; 457 reg = <0x8000 0x13c>; 458 }; 459 }; 460 }; 461}; 462