1/ { 2 #address-cells = <1>; 3 #size-cells = <1>; 4 compatible = "brcm,bcm7360"; 5 6 cpus { 7 #address-cells = <1>; 8 #size-cells = <0>; 9 10 mips-hpt-frequency = <375000000>; 11 12 cpu@0 { 13 compatible = "brcm,bmips3300"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 }; 18 19 aliases { 20 uart0 = &uart0; 21 }; 22 23 cpu_intc: interrupt-controller { 24 #address-cells = <0>; 25 compatible = "mti,cpu-interrupt-controller"; 26 27 interrupt-controller; 28 #interrupt-cells = <1>; 29 }; 30 31 clocks { 32 uart_clk: uart_clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <81000000>; 36 }; 37 38 upg_clk: upg_clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <27000000>; 42 }; 43 }; 44 45 rdb { 46 #address-cells = <1>; 47 #size-cells = <1>; 48 49 compatible = "simple-bus"; 50 ranges = <0 0x10000000 0x01000000>; 51 52 periph_intc: interrupt-controller@411400 { 53 compatible = "brcm,bcm7038-l1-intc"; 54 reg = <0x411400 0x30>; 55 56 interrupt-controller; 57 #interrupt-cells = <1>; 58 59 interrupt-parent = <&cpu_intc>; 60 interrupts = <2>; 61 }; 62 63 sun_l2_intc: interrupt-controller@403000 { 64 compatible = "brcm,l2-intc"; 65 reg = <0x403000 0x30>; 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 interrupt-parent = <&periph_intc>; 69 interrupts = <48>; 70 }; 71 72 gisb-arb@400000 { 73 compatible = "brcm,bcm7400-gisb-arb"; 74 reg = <0x400000 0xdc>; 75 native-endian; 76 interrupt-parent = <&sun_l2_intc>; 77 interrupts = <0>, <2>; 78 brcm,gisb-arb-master-mask = <0x2f3>; 79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 80 "rdc_0", "raaga_0", 81 "avd_0", "jtag_0"; 82 }; 83 84 upg_irq0_intc: interrupt-controller@406600 { 85 compatible = "brcm,bcm7120-l2-intc"; 86 reg = <0x406600 0x8>; 87 88 brcm,int-map-mask = <0x44>, <0x7000000>; 89 brcm,int-fwd-mask = <0x70000>; 90 91 interrupt-controller; 92 #interrupt-cells = <1>; 93 94 interrupt-parent = <&periph_intc>; 95 interrupts = <56>, <54>; 96 interrupt-names = "upg_main", "upg_bsc"; 97 }; 98 99 upg_aon_irq0_intc: interrupt-controller@408b80 { 100 compatible = "brcm,bcm7120-l2-intc"; 101 reg = <0x408b80 0x8>; 102 103 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; 104 brcm,int-fwd-mask = <0>; 105 brcm,irq-can-wake; 106 107 interrupt-controller; 108 #interrupt-cells = <1>; 109 110 interrupt-parent = <&periph_intc>; 111 interrupts = <57>, <55>, <59>; 112 interrupt-names = "upg_main_aon", "upg_bsc_aon", 113 "upg_spi"; 114 }; 115 116 sun_top_ctrl: syscon@404000 { 117 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon"; 118 reg = <0x404000 0x51c>; 119 native-endian; 120 }; 121 122 reboot { 123 compatible = "brcm,brcmstb-reboot"; 124 syscon = <&sun_top_ctrl 0x304 0x308>; 125 }; 126 127 uart0: serial@406800 { 128 compatible = "ns16550a"; 129 reg = <0x406800 0x20>; 130 reg-io-width = <0x4>; 131 reg-shift = <0x2>; 132 native-endian; 133 interrupt-parent = <&periph_intc>; 134 interrupts = <61>; 135 clocks = <&uart_clk>; 136 status = "disabled"; 137 }; 138 139 uart1: serial@406840 { 140 compatible = "ns16550a"; 141 reg = <0x406840 0x20>; 142 reg-io-width = <0x4>; 143 reg-shift = <0x2>; 144 native-endian; 145 interrupt-parent = <&periph_intc>; 146 interrupts = <62>; 147 clocks = <&uart_clk>; 148 status = "disabled"; 149 }; 150 151 uart2: serial@406880 { 152 compatible = "ns16550a"; 153 reg = <0x406880 0x20>; 154 reg-io-width = <0x4>; 155 reg-shift = <0x2>; 156 native-endian; 157 interrupt-parent = <&periph_intc>; 158 interrupts = <63>; 159 clocks = <&uart_clk>; 160 status = "disabled"; 161 }; 162 163 bsca: i2c@406200 { 164 clock-frequency = <390000>; 165 compatible = "brcm,brcmstb-i2c"; 166 interrupt-parent = <&upg_irq0_intc>; 167 reg = <0x406200 0x58>; 168 interrupts = <24>; 169 interrupt-names = "upg_bsca"; 170 status = "disabled"; 171 }; 172 173 bscb: i2c@406280 { 174 clock-frequency = <390000>; 175 compatible = "brcm,brcmstb-i2c"; 176 interrupt-parent = <&upg_irq0_intc>; 177 reg = <0x406280 0x58>; 178 interrupts = <25>; 179 interrupt-names = "upg_bscb"; 180 status = "disabled"; 181 }; 182 183 bscc: i2c@406300 { 184 clock-frequency = <390000>; 185 compatible = "brcm,brcmstb-i2c"; 186 interrupt-parent = <&upg_irq0_intc>; 187 reg = <0x406300 0x58>; 188 interrupts = <26>; 189 interrupt-names = "upg_bscc"; 190 status = "disabled"; 191 }; 192 193 bscd: i2c@408980 { 194 clock-frequency = <390000>; 195 compatible = "brcm,brcmstb-i2c"; 196 interrupt-parent = <&upg_aon_irq0_intc>; 197 reg = <0x408980 0x58>; 198 interrupts = <27>; 199 interrupt-names = "upg_bscd"; 200 status = "disabled"; 201 }; 202 203 pwma: pwm@406400 { 204 compatible = "brcm,bcm7038-pwm"; 205 reg = <0x406400 0x28>; 206 #pwm-cells = <2>; 207 clocks = <&upg_clk>; 208 status = "disabled"; 209 }; 210 211 aon_pm_l2_intc: interrupt-controller@408440 { 212 compatible = "brcm,l2-intc"; 213 reg = <0x408440 0x30>; 214 interrupt-controller; 215 #interrupt-cells = <1>; 216 interrupt-parent = <&periph_intc>; 217 interrupts = <50>; 218 brcm,irq-can-wake; 219 }; 220 221 upg_gio: gpio@406500 { 222 compatible = "brcm,brcmstb-gpio"; 223 reg = <0x406500 0xa0>; 224 #gpio-cells = <2>; 225 #interrupt-cells = <2>; 226 gpio-controller; 227 interrupt-controller; 228 interrupt-parent = <&upg_irq0_intc>; 229 interrupts = <6>; 230 brcm,gpio-bank-widths = <32 32 32 29 4>; 231 }; 232 233 upg_gio_aon: gpio@408c00 { 234 compatible = "brcm,brcmstb-gpio"; 235 reg = <0x408c00 0x60>; 236 #gpio-cells = <2>; 237 #interrupt-cells = <2>; 238 gpio-controller; 239 interrupt-controller; 240 interrupt-parent = <&upg_aon_irq0_intc>; 241 interrupts = <6>; 242 interrupts-extended = <&upg_aon_irq0_intc 6>, 243 <&aon_pm_l2_intc 5>; 244 wakeup-source; 245 brcm,gpio-bank-widths = <21 32 2>; 246 }; 247 248 enet0: ethernet@430000 { 249 phy-mode = "internal"; 250 phy-handle = <&phy1>; 251 mac-address = [ 00 10 18 36 23 1a ]; 252 compatible = "brcm,genet-v2"; 253 #address-cells = <0x1>; 254 #size-cells = <0x1>; 255 reg = <0x430000 0x4c8c>; 256 interrupts = <24>, <25>; 257 interrupt-parent = <&periph_intc>; 258 status = "disabled"; 259 260 mdio@e14 { 261 compatible = "brcm,genet-mdio-v2"; 262 #address-cells = <0x1>; 263 #size-cells = <0x0>; 264 reg = <0xe14 0x8>; 265 266 phy1: ethernet-phy@1 { 267 max-speed = <100>; 268 reg = <0x1>; 269 compatible = "brcm,40nm-ephy", 270 "ethernet-phy-ieee802.3-c22"; 271 }; 272 }; 273 }; 274 275 ehci0: usb@480300 { 276 compatible = "brcm,bcm7360-ehci", "generic-ehci"; 277 reg = <0x480300 0x100>; 278 native-endian; 279 interrupt-parent = <&periph_intc>; 280 interrupts = <65>; 281 status = "disabled"; 282 }; 283 284 ohci0: usb@480400 { 285 compatible = "brcm,bcm7360-ohci", "generic-ohci"; 286 reg = <0x480400 0x100>; 287 native-endian; 288 no-big-frame-no; 289 interrupt-parent = <&periph_intc>; 290 interrupts = <66>; 291 status = "disabled"; 292 }; 293 294 hif_l2_intc: interrupt-controller@411000 { 295 compatible = "brcm,l2-intc"; 296 reg = <0x411000 0x30>; 297 interrupt-controller; 298 #interrupt-cells = <1>; 299 interrupt-parent = <&periph_intc>; 300 interrupts = <30>; 301 }; 302 303 nand: nand@412800 { 304 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 reg-names = "nand"; 308 reg = <0x412800 0x400>; 309 interrupt-parent = <&hif_l2_intc>; 310 interrupts = <24>; 311 status = "disabled"; 312 }; 313 314 sata: sata@181000 { 315 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; 316 reg-names = "ahci", "top-ctrl"; 317 reg = <0x181000 0xa9c>, <0x180020 0x1c>; 318 interrupt-parent = <&periph_intc>; 319 interrupts = <86>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 status = "disabled"; 323 324 sata0: sata-port@0 { 325 reg = <0>; 326 phys = <&sata_phy0>; 327 }; 328 329 sata1: sata-port@1 { 330 reg = <1>; 331 phys = <&sata_phy1>; 332 }; 333 }; 334 335 sata_phy: sata-phy@180100 { 336 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; 337 reg = <0x180100 0x0eff>; 338 reg-names = "phy"; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 343 sata_phy0: sata-phy@0 { 344 reg = <0>; 345 #phy-cells = <0>; 346 }; 347 348 sata_phy1: sata-phy@1 { 349 reg = <1>; 350 #phy-cells = <0>; 351 }; 352 }; 353 354 sdhci0: sdhci@410000 { 355 compatible = "brcm,bcm7425-sdhci"; 356 reg = <0x410000 0x100>; 357 interrupt-parent = <&periph_intc>; 358 interrupts = <82>; 359 status = "disabled"; 360 }; 361 362 spi_l2_intc: interrupt-controller@411d00 { 363 compatible = "brcm,l2-intc"; 364 reg = <0x411d00 0x30>; 365 interrupt-controller; 366 #interrupt-cells = <1>; 367 interrupt-parent = <&periph_intc>; 368 interrupts = <31>; 369 }; 370 371 qspi: spi@413000 { 372 #address-cells = <0x1>; 373 #size-cells = <0x0>; 374 compatible = "brcm,spi-bcm-qspi", 375 "brcm,spi-brcmstb-qspi"; 376 clocks = <&upg_clk>; 377 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; 378 reg-names = "cs_reg", "hif_mspi", "bspi"; 379 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 380 interrupt-parent = <&spi_l2_intc>; 381 interrupt-names = "spi_lr_fullness_reached", 382 "spi_lr_session_aborted", 383 "spi_lr_impatient", 384 "spi_lr_session_done", 385 "spi_lr_overread", 386 "mspi_done", 387 "mspi_halted"; 388 status = "disabled"; 389 }; 390 391 mspi: spi@408a00 { 392 #address-cells = <1>; 393 #size-cells = <0>; 394 compatible = "brcm,spi-bcm-qspi", 395 "brcm,spi-brcmstb-mspi"; 396 clocks = <&upg_clk>; 397 reg = <0x408a00 0x180>; 398 reg-names = "mspi"; 399 interrupts = <0x14>; 400 interrupt-parent = <&upg_aon_irq0_intc>; 401 interrupt-names = "mspi_done"; 402 status = "disabled"; 403 }; 404 }; 405}; 406