xref: /linux/arch/mips/boot/dts/brcm/bcm7346.dtsi (revision c411ed854584a71b0e86ac3019b60e4789d88086)
1/ {
2	#address-cells = <1>;
3	#size-cells = <1>;
4	compatible = "brcm,bcm7346";
5
6	cpus {
7		#address-cells = <1>;
8		#size-cells = <0>;
9
10		mips-hpt-frequency = <163125000>;
11
12		cpu@0 {
13			compatible = "brcm,bmips5000";
14			device_type = "cpu";
15			reg = <0>;
16		};
17
18		cpu@1 {
19			compatible = "brcm,bmips5000";
20			device_type = "cpu";
21			reg = <1>;
22		};
23	};
24
25	aliases {
26		uart0 = &uart0;
27	};
28
29	cpu_intc: interrupt-controller {
30		#address-cells = <0>;
31		compatible = "mti,cpu-interrupt-controller";
32
33		interrupt-controller;
34		#interrupt-cells = <1>;
35	};
36
37	clocks {
38		uart_clk: uart_clk {
39			compatible = "fixed-clock";
40			#clock-cells = <0>;
41			clock-frequency = <81000000>;
42		};
43
44		upg_clk: upg_clk {
45			compatible = "fixed-clock";
46			#clock-cells = <0>;
47			clock-frequency = <27000000>;
48		};
49	};
50
51	rdb {
52		#address-cells = <1>;
53		#size-cells = <1>;
54
55		compatible = "simple-bus";
56		ranges = <0 0x10000000 0x01000000>;
57
58		periph_intc: interrupt-controller@411400 {
59			compatible = "brcm,bcm7038-l1-intc";
60			reg = <0x411400 0x30>, <0x411600 0x30>;
61
62			interrupt-controller;
63			#interrupt-cells = <1>;
64
65			interrupt-parent = <&cpu_intc>;
66			interrupts = <2>, <3>;
67		};
68
69		sun_l2_intc: interrupt-controller@403000 {
70			compatible = "brcm,l2-intc";
71			reg = <0x403000 0x30>;
72			interrupt-controller;
73			#interrupt-cells = <1>;
74			interrupt-parent = <&periph_intc>;
75			interrupts = <51>;
76		};
77
78		gisb-arb@400000 {
79			compatible = "brcm,bcm7400-gisb-arb";
80			reg = <0x400000 0xdc>;
81			native-endian;
82			interrupt-parent = <&sun_l2_intc>;
83			interrupts = <0>, <2>;
84			brcm,gisb-arb-master-mask = <0x673>;
85			brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
86						     "rdc_0", "raaga_0",
87						     "jtag_0", "svd_0";
88		};
89
90		upg_irq0_intc: interrupt-controller@406780 {
91			compatible = "brcm,bcm7120-l2-intc";
92			reg = <0x406780 0x8>;
93
94			brcm,int-map-mask = <0x44>, <0xf000000>;
95			brcm,int-fwd-mask = <0x70000>;
96
97			interrupt-controller;
98			#interrupt-cells = <1>;
99
100			interrupt-parent = <&periph_intc>;
101			interrupts = <59>, <57>;
102			interrupt-names = "upg_main", "upg_bsc";
103		};
104
105		upg_aon_irq0_intc: interrupt-controller@408b80 {
106			compatible = "brcm,bcm7120-l2-intc";
107			reg = <0x408b80 0x8>;
108
109			brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
110			brcm,int-fwd-mask = <0>;
111			brcm,irq-can-wake;
112
113			interrupt-controller;
114			#interrupt-cells = <1>;
115
116			interrupt-parent = <&periph_intc>;
117			interrupts = <60>, <58>, <62>;
118			interrupt-names = "upg_main_aon", "upg_bsc_aon",
119					  "upg_spi";
120		};
121
122		sun_top_ctrl: syscon@404000 {
123			compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
124			reg = <0x404000 0x51c>;
125			native-endian;
126		};
127
128		reboot {
129			compatible = "brcm,brcmstb-reboot";
130			syscon = <&sun_top_ctrl 0x304 0x308>;
131		};
132
133		uart0: serial@406900 {
134			compatible = "ns16550a";
135			reg = <0x406900 0x20>;
136			reg-io-width = <0x4>;
137			reg-shift = <0x2>;
138			native-endian;
139			interrupt-parent = <&periph_intc>;
140			interrupts = <64>;
141			clocks = <&uart_clk>;
142			status = "disabled";
143		};
144
145		uart1: serial@406940 {
146			compatible = "ns16550a";
147			reg = <0x406940 0x20>;
148			reg-io-width = <0x4>;
149			reg-shift = <0x2>;
150			native-endian;
151			interrupt-parent = <&periph_intc>;
152			interrupts = <65>;
153			clocks = <&uart_clk>;
154			status = "disabled";
155		};
156
157		uart2: serial@406980 {
158			compatible = "ns16550a";
159			reg = <0x406980 0x20>;
160			reg-io-width = <0x4>;
161			reg-shift = <0x2>;
162			native-endian;
163			interrupt-parent = <&periph_intc>;
164			interrupts = <66>;
165			clocks = <&uart_clk>;
166			status = "disabled";
167		};
168
169		bsca: i2c@406200 {
170		      clock-frequency = <390000>;
171		      compatible = "brcm,brcmstb-i2c";
172		      interrupt-parent = <&upg_irq0_intc>;
173		      reg = <0x406200 0x58>;
174		      interrupts = <24>;
175		      interrupt-names = "upg_bsca";
176		      status = "disabled";
177		};
178
179		bscb: i2c@406280 {
180		      clock-frequency = <390000>;
181		      compatible = "brcm,brcmstb-i2c";
182		      interrupt-parent = <&upg_irq0_intc>;
183		      reg = <0x406280 0x58>;
184		      interrupts = <25>;
185		      interrupt-names = "upg_bscb";
186		      status = "disabled";
187		};
188
189		bscc: i2c@406300 {
190		      clock-frequency = <390000>;
191		      compatible = "brcm,brcmstb-i2c";
192		      interrupt-parent = <&upg_irq0_intc>;
193		      reg = <0x406300 0x58>;
194		      interrupts = <26>;
195		      interrupt-names = "upg_bscc";
196		      status = "disabled";
197		};
198
199		bscd: i2c@406380 {
200		      clock-frequency = <390000>;
201		      compatible = "brcm,brcmstb-i2c";
202		      interrupt-parent = <&upg_irq0_intc>;
203		      reg = <0x406380 0x58>;
204		      interrupts = <27>;
205		      interrupt-names = "upg_bscd";
206		      status = "disabled";
207		};
208
209		bsce: i2c@408980 {
210		      clock-frequency = <390000>;
211		      compatible = "brcm,brcmstb-i2c";
212		      interrupt-parent = <&upg_aon_irq0_intc>;
213		      reg = <0x408980 0x58>;
214		      interrupts = <27>;
215		      interrupt-names = "upg_bsce";
216		      status = "disabled";
217		};
218
219		pwma: pwm@406580 {
220			compatible = "brcm,bcm7038-pwm";
221			reg = <0x406580 0x28>;
222			#pwm-cells = <2>;
223			clocks = <&upg_clk>;
224			status = "disabled";
225		};
226
227		pwmb: pwm@406800 {
228			compatible = "brcm,bcm7038-pwm";
229			reg = <0x406800 0x28>;
230			#pwm-cells = <2>;
231			clocks = <&upg_clk>;
232			status = "disabled";
233		};
234
235		aon_pm_l2_intc: interrupt-controller@408440 {
236			compatible = "brcm,l2-intc";
237			reg = <0x408440 0x30>;
238			interrupt-controller;
239			#interrupt-cells = <1>;
240			interrupt-parent = <&periph_intc>;
241			interrupts = <53>;
242			brcm,irq-can-wake;
243		};
244
245		upg_gio: gpio@406700 {
246			compatible = "brcm,brcmstb-gpio";
247			reg = <0x406700 0x60>;
248			#gpio-cells = <2>;
249			#interrupt-cells = <2>;
250			gpio-controller;
251			interrupt-controller;
252			interrupt-parent = <&upg_irq0_intc>;
253			interrupts = <6>;
254			brcm,gpio-bank-widths = <32 32 16>;
255		};
256
257		upg_gio_aon: gpio@408c00 {
258			compatible = "brcm,brcmstb-gpio";
259			reg = <0x408c00 0x60>;
260			#gpio-cells = <2>;
261			#interrupt-cells = <2>;
262			gpio-controller;
263			interrupt-controller;
264			interrupt-parent = <&upg_aon_irq0_intc>;
265			interrupts = <6>;
266			interrupts-extended = <&upg_aon_irq0_intc 6>,
267					      <&aon_pm_l2_intc 5>;
268			wakeup-source;
269			brcm,gpio-bank-widths = <27 32 2>;
270		};
271
272		enet0: ethernet@430000 {
273			phy-mode = "internal";
274			phy-handle = <&phy1>;
275			mac-address = [ 00 10 18 36 23 1a ];
276			compatible = "brcm,genet-v2";
277			#address-cells = <0x1>;
278			#size-cells = <0x1>;
279			reg = <0x430000 0x4c8c>;
280			interrupts = <24>, <25>;
281			interrupt-parent = <&periph_intc>;
282			status = "disabled";
283
284			mdio@e14 {
285				compatible = "brcm,genet-mdio-v2";
286				#address-cells = <0x1>;
287				#size-cells = <0x0>;
288				reg = <0xe14 0x8>;
289
290				phy1: ethernet-phy@1 {
291					max-speed = <100>;
292					reg = <0x1>;
293					compatible = "brcm,40nm-ephy",
294						"ethernet-phy-ieee802.3-c22";
295				};
296			};
297		};
298
299		ehci0: usb@480300 {
300			compatible = "brcm,bcm7346-ehci", "generic-ehci";
301			reg = <0x480300 0x100>;
302			native-endian;
303			interrupt-parent = <&periph_intc>;
304			interrupts = <68>;
305			status = "disabled";
306		};
307
308		ohci0: usb@480400 {
309			compatible = "brcm,bcm7346-ohci", "generic-ohci";
310			reg = <0x480400 0x100>;
311			native-endian;
312			no-big-frame-no;
313			interrupt-parent = <&periph_intc>;
314			interrupts = <70>;
315			status = "disabled";
316		};
317
318		ehci1: usb@480500 {
319			compatible = "brcm,bcm7346-ehci", "generic-ehci";
320			reg = <0x480500 0x100>;
321			native-endian;
322			interrupt-parent = <&periph_intc>;
323			interrupts = <69>;
324			status = "disabled";
325		};
326
327		ohci1: usb@480600 {
328			compatible = "brcm,bcm7346-ohci", "generic-ohci";
329			reg = <0x480600 0x100>;
330			native-endian;
331			no-big-frame-no;
332			interrupt-parent = <&periph_intc>;
333			interrupts = <71>;
334			status = "disabled";
335		};
336
337		ehci2: usb@490300 {
338			compatible = "brcm,bcm7346-ehci", "generic-ehci";
339			reg = <0x490300 0x100>;
340			native-endian;
341			interrupt-parent = <&periph_intc>;
342			interrupts = <73>;
343			status = "disabled";
344		};
345
346		ohci2: usb@490400 {
347			compatible = "brcm,bcm7346-ohci", "generic-ohci";
348			reg = <0x490400 0x100>;
349			native-endian;
350			no-big-frame-no;
351			interrupt-parent = <&periph_intc>;
352			interrupts = <75>;
353			status = "disabled";
354		};
355
356		ehci3: usb@490500 {
357			compatible = "brcm,bcm7346-ehci", "generic-ehci";
358			reg = <0x490500 0x100>;
359			native-endian;
360			interrupt-parent = <&periph_intc>;
361			interrupts = <74>;
362			status = "disabled";
363		};
364
365		ohci3: usb@490600 {
366			compatible = "brcm,bcm7346-ohci", "generic-ohci";
367			reg = <0x490600 0x100>;
368			native-endian;
369			no-big-frame-no;
370			interrupt-parent = <&periph_intc>;
371			interrupts = <76>;
372			status = "disabled";
373		};
374
375		hif_l2_intc: interrupt-controller@411000 {
376			compatible = "brcm,l2-intc";
377			reg = <0x411000 0x30>;
378			interrupt-controller;
379			#interrupt-cells = <1>;
380			interrupt-parent = <&periph_intc>;
381			interrupts = <30>;
382		};
383
384		nand: nand@412800 {
385			compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
386			#address-cells = <1>;
387			#size-cells = <0>;
388			reg-names = "nand";
389			reg = <0x412800 0x400>;
390			interrupt-parent = <&hif_l2_intc>;
391			interrupts = <24>;
392			status = "disabled";
393		};
394
395		sata: sata@181000 {
396			compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
397			reg-names = "ahci", "top-ctrl";
398			reg = <0x181000 0xa9c>, <0x180020 0x1c>;
399			interrupt-parent = <&periph_intc>;
400			interrupts = <40>;
401			#address-cells = <1>;
402			#size-cells = <0>;
403			status = "disabled";
404
405			sata0: sata-port@0 {
406				reg = <0>;
407				phys = <&sata_phy0>;
408			};
409
410			sata1: sata-port@1 {
411				reg = <1>;
412				phys = <&sata_phy1>;
413			};
414		};
415
416		sata_phy: sata-phy@180100 {
417			compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
418			reg = <0x180100 0x0eff>;
419			reg-names = "phy";
420			#address-cells = <1>;
421			#size-cells = <0>;
422			status = "disabled";
423
424			sata_phy0: sata-phy@0 {
425				reg = <0>;
426				#phy-cells = <0>;
427			};
428
429			sata_phy1: sata-phy@1 {
430				reg = <1>;
431				#phy-cells = <0>;
432			};
433		};
434
435		sdhci0: sdhci@413500 {
436			compatible = "brcm,bcm7425-sdhci";
437			reg = <0x413500 0x100>;
438			interrupt-parent = <&periph_intc>;
439			interrupts = <85>;
440			status = "disabled";
441		};
442
443		spi_l2_intc: interrupt-controller@411d00 {
444			compatible = "brcm,l2-intc";
445			reg = <0x411d00 0x30>;
446			interrupt-controller;
447			#interrupt-cells = <1>;
448			interrupt-parent = <&periph_intc>;
449			interrupts = <31>;
450		};
451
452		qspi: spi@413000 {
453			#address-cells = <0x1>;
454			#size-cells = <0x0>;
455			compatible = "brcm,spi-bcm-qspi",
456				     "brcm,spi-brcmstb-qspi";
457			clocks = <&upg_clk>;
458			reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
459			reg-names = "cs_reg", "hif_mspi", "bspi";
460			interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
461			interrupt-parent = <&spi_l2_intc>;
462			interrupt-names = "spi_lr_fullness_reached",
463					  "spi_lr_session_aborted",
464					  "spi_lr_impatient",
465					  "spi_lr_session_done",
466					  "spi_lr_overread",
467					  "mspi_done",
468					  "mspi_halted";
469			status = "disabled";
470		};
471
472		mspi: spi@408a00 {
473			#address-cells = <1>;
474			#size-cells = <0>;
475			compatible = "brcm,spi-bcm-qspi",
476				     "brcm,spi-brcmstb-mspi";
477			clocks = <&upg_clk>;
478			reg = <0x408a00 0x180>;
479			reg-names = "mspi";
480			interrupts = <0x14>;
481			interrupt-parent = <&upg_aon_irq0_intc>;
482			interrupt-names = "mspi_done";
483			status = "disabled";
484		};
485	};
486};
487