1// SPDX-License-Identifier: GPL-2.0 2 3#include "dt-bindings/clock/bcm6368-clock.h" 4#include "dt-bindings/reset/bcm6368-reset.h" 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "brcm,bcm6368"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 mips-hpt-frequency = <200000000>; 16 brcm,bmips-cbr-reg = <0xff400000>; 17 18 cpu@0 { 19 compatible = "brcm,bmips4350"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 24 cpu@1 { 25 compatible = "brcm,bmips4350"; 26 device_type = "cpu"; 27 reg = <1>; 28 }; 29 }; 30 31 clocks { 32 periph_osc: periph-osc { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <50000000>; 36 clock-output-names = "periph"; 37 }; 38 }; 39 40 aliases { 41 nflash = &nflash; 42 pflash = &pflash; 43 serial0 = &uart0; 44 serial1 = &uart1; 45 spi0 = &lsspi; 46 }; 47 48 cpu_intc: interrupt-controller { 49 #address-cells = <0>; 50 compatible = "mti,cpu-interrupt-controller"; 51 52 interrupt-controller; 53 #interrupt-cells = <1>; 54 }; 55 56 ubus { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 60 compatible = "simple-bus"; 61 ranges; 62 63 periph_clk: clock-controller@10000004 { 64 compatible = "brcm,bcm6368-clocks"; 65 reg = <0x10000004 0x4>; 66 #clock-cells = <1>; 67 }; 68 69 pll_cntl: syscon@100000008 { 70 compatible = "syscon"; 71 reg = <0x10000008 0x4>; 72 native-endian; 73 74 reboot { 75 compatible = "syscon-reboot"; 76 offset = <0x0>; 77 mask = <0x1>; 78 }; 79 }; 80 81 periph_rst: reset-controller@10000010 { 82 compatible = "brcm,bcm6345-reset"; 83 reg = <0x10000010 0x4>; 84 #reset-cells = <1>; 85 }; 86 87 periph_intc: interrupt-controller@10000020 { 88 compatible = "brcm,bcm6345-l1-intc"; 89 reg = <0x10000020 0x10>, 90 <0x10000030 0x10>; 91 92 interrupt-controller; 93 #interrupt-cells = <1>; 94 95 interrupt-parent = <&cpu_intc>; 96 interrupts = <2>, <3>; 97 }; 98 99 wdt: watchdog@1000005c { 100 compatible = "brcm,bcm7038-wdt"; 101 reg = <0x1000005c 0xc>; 102 103 clocks = <&periph_osc>; 104 clock-names = "refclk"; 105 106 timeout-sec = <30>; 107 }; 108 109 leds0: led-controller@100000d0 { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 compatible = "brcm,bcm6358-leds"; 113 reg = <0x100000d0 0x8>; 114 115 status = "disabled"; 116 }; 117 118 uart0: serial@10000100 { 119 compatible = "brcm,bcm6345-uart"; 120 reg = <0x10000100 0x18>; 121 122 interrupt-parent = <&periph_intc>; 123 interrupts = <2>; 124 125 clocks = <&periph_osc>; 126 clock-names = "refclk"; 127 128 status = "disabled"; 129 }; 130 131 uart1: serial@10000120 { 132 compatible = "brcm,bcm6345-uart"; 133 reg = <0x10000120 0x18>; 134 135 interrupt-parent = <&periph_intc>; 136 interrupts = <3>; 137 138 clocks = <&periph_osc>; 139 clock-names = "refclk"; 140 141 status = "disabled"; 142 }; 143 144 nflash: nand@10000200 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 compatible = "brcm,nand-bcm6368", 148 "brcm,brcmnand-v2.1", 149 "brcm,brcmnand"; 150 reg = <0x10000200 0x180>, 151 <0x10000600 0x200>, 152 <0x10000070 0x10>; 153 reg-names = "nand", 154 "nand-cache", 155 "nand-int-base"; 156 157 interrupt-parent = <&periph_intc>; 158 interrupts = <10>; 159 160 clocks = <&periph_clk BCM6368_CLK_NAND>; 161 clock-names = "nand"; 162 163 status = "disabled"; 164 }; 165 166 lsspi: spi@10000800 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 compatible = "brcm,bcm6358-spi"; 170 reg = <0x10000800 0x70c>; 171 172 interrupt-parent = <&periph_intc>; 173 interrupts = <1>; 174 175 clocks = <&periph_clk BCM6368_CLK_SPI>; 176 clock-names = "spi"; 177 178 resets = <&periph_rst BCM6368_RST_SPI>; 179 reset-names = "spi"; 180 181 status = "disabled"; 182 }; 183 184 ehci: usb@10001500 { 185 compatible = "brcm,bcm6368-ehci", "generic-ehci"; 186 reg = <0x10001500 0x100>; 187 big-endian; 188 189 interrupt-parent = <&periph_intc>; 190 interrupts = <7>; 191 192 phys = <&usbh 0>; 193 phy-names = "usb"; 194 195 status = "disabled"; 196 }; 197 198 ohci: usb@10001600 { 199 compatible = "brcm,bcm6368-ohci", "generic-ohci"; 200 reg = <0x10001600 0x100>; 201 big-endian; 202 no-big-frame-no; 203 204 interrupt-parent = <&periph_intc>; 205 interrupts = <5>; 206 207 phys = <&usbh 0>; 208 phy-names = "usb"; 209 210 status = "disabled"; 211 }; 212 213 usbh: usb-phy@10001700 { 214 compatible = "brcm,bcm6368-usbh-phy"; 215 reg = <0x10001700 0x38>; 216 #phy-cells = <1>; 217 218 clocks = <&periph_clk BCM6368_CLK_USBH>; 219 clock-names = "usbh"; 220 221 resets = <&periph_rst BCM6368_RST_USBH>; 222 reset-names = "usbh"; 223 224 status = "disabled"; 225 }; 226 227 random: rng@10004180 { 228 compatible = "brcm,bcm6368-rng"; 229 reg = <0x10004180 0x14>; 230 231 clocks = <&periph_clk BCM6368_CLK_IPSEC>; 232 clock-names = "ipsec"; 233 234 resets = <&periph_rst BCM6368_RST_IPSEC>; 235 reset-names = "ipsec"; 236 }; 237 }; 238 239 pflash: nor@18000000 { 240 #address-cells = <1>; 241 #size-cells = <1>; 242 compatible = "cfi-flash"; 243 reg = <0x18000000 0x2000000>; 244 bank-width = <2>; 245 246 status = "disabled"; 247 }; 248}; 249