1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com> 8 */ 9 10 #include <linux/init.h> 11 #include <linux/bitops.h> 12 #include <linux/bootmem.h> 13 #include <linux/clk-provider.h> 14 #include <linux/ioport.h> 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/of_fdt.h> 19 #include <linux/of_platform.h> 20 #include <linux/smp.h> 21 #include <asm/addrspace.h> 22 #include <asm/bmips.h> 23 #include <asm/bootinfo.h> 24 #include <asm/cpu-type.h> 25 #include <asm/mipsregs.h> 26 #include <asm/prom.h> 27 #include <asm/smp-ops.h> 28 #include <asm/time.h> 29 #include <asm/traps.h> 30 31 #define RELO_NORMAL_VEC BIT(18) 32 33 #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) 34 #define BCM6328_TP1_DISABLED BIT(9) 35 36 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; 37 38 struct bmips_quirk { 39 const char *compatible; 40 void (*quirk_fn)(void); 41 }; 42 43 static void kbase_setup(void) 44 { 45 __raw_writel(kbase | RELO_NORMAL_VEC, 46 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1); 47 ebase = kbase; 48 } 49 50 static void bcm3384_viper_quirks(void) 51 { 52 /* 53 * Some experimental CM boxes are set up to let CM own the Viper TP0 54 * and let Linux own TP1. This requires moving the kernel 55 * load address to a non-conflicting region (e.g. via 56 * CONFIG_PHYSICAL_START) and supplying an alternate DTB. 57 * If we detect this condition, we need to move the MIPS exception 58 * vectors up to an area that we own. 59 * 60 * This is distinct from the OTHER special case mentioned in 61 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our 62 * logical CPU#1). For the Viper TP1 case, SMP is off limits. 63 * 64 * Also note that many BMIPS435x CPUs do not have a 65 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just 66 * write VMLINUX_LOAD_ADDRESS into that register on every SoC. 67 */ 68 board_ebase_setup = &kbase_setup; 69 bmips_smp_enabled = 0; 70 } 71 72 static void bcm63xx_fixup_cpu1(void) 73 { 74 /* 75 * The bootloader has set up the CPU1 reset vector at 76 * 0xa000_0200. 77 * This conflicts with the special interrupt vector (IV). 78 * The bootloader has also set up CPU1 to respond to the wrong 79 * IPI interrupt. 80 * Here we will start up CPU1 in the background and ask it to 81 * reconfigure itself then go back to sleep. 82 */ 83 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); 84 __sync(); 85 set_c0_cause(C_SW0); 86 cpumask_set_cpu(1, &bmips_booted_mask); 87 } 88 89 static void bcm6328_quirks(void) 90 { 91 /* Check CPU1 status in OTP (it is usually disabled) */ 92 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED) 93 bmips_smp_enabled = 0; 94 else 95 bcm63xx_fixup_cpu1(); 96 } 97 98 static void bcm6368_quirks(void) 99 { 100 bcm63xx_fixup_cpu1(); 101 } 102 103 static const struct bmips_quirk bmips_quirk_list[] = { 104 { "brcm,bcm3384-viper", &bcm3384_viper_quirks }, 105 { "brcm,bcm33843-viper", &bcm3384_viper_quirks }, 106 { "brcm,bcm6328", &bcm6328_quirks }, 107 { "brcm,bcm6368", &bcm6368_quirks }, 108 { "brcm,bcm63168", &bcm6368_quirks }, 109 { }, 110 }; 111 112 void __init prom_init(void) 113 { 114 bmips_cpu_setup(); 115 register_bmips_smp_ops(); 116 } 117 118 void __init prom_free_prom_memory(void) 119 { 120 } 121 122 const char *get_system_type(void) 123 { 124 return "Generic BMIPS kernel"; 125 } 126 127 void __init plat_time_init(void) 128 { 129 struct device_node *np; 130 u32 freq; 131 132 np = of_find_node_by_name(NULL, "cpus"); 133 if (!np) 134 panic("missing 'cpus' DT node"); 135 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) 136 panic("missing 'mips-hpt-frequency' property"); 137 of_node_put(np); 138 139 mips_hpt_frequency = freq; 140 } 141 142 void __init plat_mem_setup(void) 143 { 144 void *dtb; 145 const struct bmips_quirk *q; 146 147 set_io_port_base(0); 148 ioport_resource.start = 0; 149 ioport_resource.end = ~0; 150 151 /* intended to somewhat resemble ARM; see Documentation/arm/Booting */ 152 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) 153 dtb = phys_to_virt(fw_arg2); 154 else if (fw_arg0 == -2) /* UHI interface */ 155 dtb = (void *)fw_arg1; 156 else if (__dtb_start != __dtb_end) 157 dtb = (void *)__dtb_start; 158 else 159 panic("no dtb found"); 160 161 __dt_setup_arch(dtb); 162 163 for (q = bmips_quirk_list; q->quirk_fn; q++) { 164 if (of_flat_dt_is_compatible(of_get_flat_dt_root(), 165 q->compatible)) { 166 q->quirk_fn(); 167 } 168 } 169 } 170 171 void __init device_tree_init(void) 172 { 173 struct device_node *np; 174 175 unflatten_and_copy_device_tree(); 176 177 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ 178 np = of_find_node_by_name(NULL, "cpus"); 179 if (np && of_get_available_child_count(np) <= 1) 180 bmips_smp_enabled = 0; 181 of_node_put(np); 182 } 183 184 int __init plat_of_setup(void) 185 { 186 return __dt_register_buses("simple-bus", NULL); 187 } 188 189 arch_initcall(plat_of_setup); 190 191 static int __init plat_dev_init(void) 192 { 193 of_clk_init(NULL); 194 return 0; 195 } 196 197 device_initcall(plat_dev_init); 198