1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com> 8 */ 9 10 #include <linux/init.h> 11 #include <linux/bitops.h> 12 #include <linux/bootmem.h> 13 #include <linux/clk-provider.h> 14 #include <linux/ioport.h> 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/of_fdt.h> 19 #include <linux/of_platform.h> 20 #include <linux/libfdt.h> 21 #include <linux/smp.h> 22 #include <asm/addrspace.h> 23 #include <asm/bmips.h> 24 #include <asm/bootinfo.h> 25 #include <asm/cpu-type.h> 26 #include <asm/mipsregs.h> 27 #include <asm/prom.h> 28 #include <asm/smp-ops.h> 29 #include <asm/time.h> 30 #include <asm/traps.h> 31 32 #define RELO_NORMAL_VEC BIT(18) 33 34 #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) 35 #define BCM6328_TP1_DISABLED BIT(9) 36 37 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; 38 39 struct bmips_quirk { 40 const char *compatible; 41 void (*quirk_fn)(void); 42 }; 43 44 static void kbase_setup(void) 45 { 46 __raw_writel(kbase | RELO_NORMAL_VEC, 47 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1); 48 ebase = kbase; 49 } 50 51 static void bcm3384_viper_quirks(void) 52 { 53 /* 54 * Some experimental CM boxes are set up to let CM own the Viper TP0 55 * and let Linux own TP1. This requires moving the kernel 56 * load address to a non-conflicting region (e.g. via 57 * CONFIG_PHYSICAL_START) and supplying an alternate DTB. 58 * If we detect this condition, we need to move the MIPS exception 59 * vectors up to an area that we own. 60 * 61 * This is distinct from the OTHER special case mentioned in 62 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our 63 * logical CPU#1). For the Viper TP1 case, SMP is off limits. 64 * 65 * Also note that many BMIPS435x CPUs do not have a 66 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just 67 * write VMLINUX_LOAD_ADDRESS into that register on every SoC. 68 */ 69 board_ebase_setup = &kbase_setup; 70 bmips_smp_enabled = 0; 71 } 72 73 static void bcm63xx_fixup_cpu1(void) 74 { 75 /* 76 * The bootloader has set up the CPU1 reset vector at 77 * 0xa000_0200. 78 * This conflicts with the special interrupt vector (IV). 79 * The bootloader has also set up CPU1 to respond to the wrong 80 * IPI interrupt. 81 * Here we will start up CPU1 in the background and ask it to 82 * reconfigure itself then go back to sleep. 83 */ 84 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); 85 __sync(); 86 set_c0_cause(C_SW0); 87 cpumask_set_cpu(1, &bmips_booted_mask); 88 } 89 90 static void bcm6328_quirks(void) 91 { 92 /* Check CPU1 status in OTP (it is usually disabled) */ 93 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED) 94 bmips_smp_enabled = 0; 95 else 96 bcm63xx_fixup_cpu1(); 97 } 98 99 static void bcm6358_quirks(void) 100 { 101 /* 102 * BCM3368/BCM6358 need special handling for their shared TLB, so 103 * disable SMP for now 104 */ 105 bmips_smp_enabled = 0; 106 } 107 108 static void bcm6368_quirks(void) 109 { 110 bcm63xx_fixup_cpu1(); 111 } 112 113 static const struct bmips_quirk bmips_quirk_list[] = { 114 { "brcm,bcm3368", &bcm6358_quirks }, 115 { "brcm,bcm3384-viper", &bcm3384_viper_quirks }, 116 { "brcm,bcm33843-viper", &bcm3384_viper_quirks }, 117 { "brcm,bcm6328", &bcm6328_quirks }, 118 { "brcm,bcm6358", &bcm6358_quirks }, 119 { "brcm,bcm6362", &bcm6368_quirks }, 120 { "brcm,bcm6368", &bcm6368_quirks }, 121 { "brcm,bcm63168", &bcm6368_quirks }, 122 { "brcm,bcm63268", &bcm6368_quirks }, 123 { }, 124 }; 125 126 void __init prom_init(void) 127 { 128 bmips_cpu_setup(); 129 register_bmips_smp_ops(); 130 } 131 132 void __init prom_free_prom_memory(void) 133 { 134 } 135 136 const char *get_system_type(void) 137 { 138 return "Generic BMIPS kernel"; 139 } 140 141 void __init plat_time_init(void) 142 { 143 struct device_node *np; 144 u32 freq; 145 146 np = of_find_node_by_name(NULL, "cpus"); 147 if (!np) 148 panic("missing 'cpus' DT node"); 149 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) 150 panic("missing 'mips-hpt-frequency' property"); 151 of_node_put(np); 152 153 mips_hpt_frequency = freq; 154 } 155 156 extern const char __appended_dtb; 157 158 void __init plat_mem_setup(void) 159 { 160 void *dtb; 161 const struct bmips_quirk *q; 162 163 set_io_port_base(0); 164 ioport_resource.start = 0; 165 ioport_resource.end = ~0; 166 167 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB 168 if (!fdt_check_header(&__appended_dtb)) 169 dtb = (void *)&__appended_dtb; 170 else 171 #endif 172 /* intended to somewhat resemble ARM; see Documentation/arm/Booting */ 173 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) 174 dtb = phys_to_virt(fw_arg2); 175 else if (fw_passed_dtb) /* UHI interface */ 176 dtb = (void *)fw_passed_dtb; 177 else if (__dtb_start != __dtb_end) 178 dtb = (void *)__dtb_start; 179 else 180 panic("no dtb found"); 181 182 __dt_setup_arch(dtb); 183 184 for (q = bmips_quirk_list; q->quirk_fn; q++) { 185 if (of_flat_dt_is_compatible(of_get_flat_dt_root(), 186 q->compatible)) { 187 q->quirk_fn(); 188 } 189 } 190 } 191 192 void __init device_tree_init(void) 193 { 194 struct device_node *np; 195 196 unflatten_and_copy_device_tree(); 197 198 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ 199 np = of_find_node_by_name(NULL, "cpus"); 200 if (np && of_get_available_child_count(np) <= 1) 201 bmips_smp_enabled = 0; 202 of_node_put(np); 203 } 204 205 int __init plat_of_setup(void) 206 { 207 return __dt_register_buses("simple-bus", NULL); 208 } 209 210 arch_initcall(plat_of_setup); 211 212 static int __init plat_dev_init(void) 213 { 214 of_clk_init(NULL); 215 return 0; 216 } 217 218 device_initcall(plat_dev_init); 219