1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com> 8 */ 9 10 #include <linux/init.h> 11 #include <linux/bitops.h> 12 #include <linux/memblock.h> 13 #include <linux/ioport.h> 14 #include <linux/kernel.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/of_clk.h> 18 #include <linux/of_fdt.h> 19 #include <linux/libfdt.h> 20 #include <linux/smp.h> 21 #include <asm/addrspace.h> 22 #include <asm/bmips.h> 23 #include <asm/bootinfo.h> 24 #include <asm/cpu-type.h> 25 #include <asm/mipsregs.h> 26 #include <asm/prom.h> 27 #include <asm/smp-ops.h> 28 #include <asm/time.h> 29 #include <asm/traps.h> 30 #include <asm/fw/cfe/cfe_api.h> 31 32 #define RELO_NORMAL_VEC BIT(18) 33 34 #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) 35 #define BCM6328_TP1_DISABLED BIT(9) 36 37 /* CBR addr doesn't change and we can cache it */ 38 void __iomem *bmips_cbr_addr __read_mostly; 39 40 extern bool bmips_rac_flush_disable; 41 42 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; 43 44 struct bmips_quirk { 45 const char *compatible; 46 void (*quirk_fn)(void); 47 }; 48 49 static void kbase_setup(void) 50 { 51 __raw_writel(kbase | RELO_NORMAL_VEC, 52 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1); 53 ebase = kbase; 54 } 55 56 static void bcm3384_viper_quirks(void) 57 { 58 /* 59 * Some experimental CM boxes are set up to let CM own the Viper TP0 60 * and let Linux own TP1. This requires moving the kernel 61 * load address to a non-conflicting region (e.g. via 62 * CONFIG_PHYSICAL_START) and supplying an alternate DTB. 63 * If we detect this condition, we need to move the MIPS exception 64 * vectors up to an area that we own. 65 * 66 * This is distinct from the OTHER special case mentioned in 67 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our 68 * logical CPU#1). For the Viper TP1 case, SMP is off limits. 69 * 70 * Also note that many BMIPS435x CPUs do not have a 71 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just 72 * write VMLINUX_LOAD_ADDRESS into that register on every SoC. 73 */ 74 board_ebase_setup = &kbase_setup; 75 bmips_smp_enabled = 0; 76 } 77 78 static void bcm63xx_fixup_cpu1(void) 79 { 80 /* 81 * The bootloader has set up the CPU1 reset vector at 82 * 0xa000_0200. 83 * This conflicts with the special interrupt vector (IV). 84 * The bootloader has also set up CPU1 to respond to the wrong 85 * IPI interrupt. 86 * Here we will start up CPU1 in the background and ask it to 87 * reconfigure itself then go back to sleep. 88 */ 89 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); 90 __sync(); 91 set_c0_cause(C_SW0); 92 cpumask_set_cpu(1, &bmips_booted_mask); 93 } 94 95 static void bcm6328_quirks(void) 96 { 97 /* Check CPU1 status in OTP (it is usually disabled) */ 98 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED) 99 bmips_smp_enabled = 0; 100 else 101 bcm63xx_fixup_cpu1(); 102 } 103 104 static void bcm6358_quirks(void) 105 { 106 /* 107 * BCM3368/BCM6358 need special handling for their shared TLB, so 108 * disable SMP for now 109 */ 110 bmips_smp_enabled = 0; 111 112 /* 113 * RAC flush causes kernel panics on BCM6358 when booting from TP1 114 * because the bootloader is not initializing it properly. 115 */ 116 bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || 117 !!bmips_cbr_addr; 118 } 119 120 static void bcm6368_quirks(void) 121 { 122 bcm63xx_fixup_cpu1(); 123 } 124 125 static const struct bmips_quirk bmips_quirk_list[] = { 126 { "brcm,bcm3368", &bcm6358_quirks }, 127 { "brcm,bcm3384-viper", &bcm3384_viper_quirks }, 128 { "brcm,bcm33843-viper", &bcm3384_viper_quirks }, 129 { "brcm,bcm6328", &bcm6328_quirks }, 130 { "brcm,bcm6358", &bcm6358_quirks }, 131 { "brcm,bcm6362", &bcm6368_quirks }, 132 { "brcm,bcm6368", &bcm6368_quirks }, 133 { "brcm,bcm63168", &bcm6368_quirks }, 134 { "brcm,bcm63268", &bcm6368_quirks }, 135 { }, 136 }; 137 138 static void __init bmips_init_cfe(void) 139 { 140 cfe_seal = fw_arg3; 141 142 if (cfe_seal != CFE_EPTSEAL) 143 return; 144 145 cfe_init(fw_arg0, fw_arg2); 146 } 147 148 void __init prom_init(void) 149 { 150 /* Cache CBR addr before CPU/DMA setup */ 151 bmips_cbr_addr = BMIPS_GET_CBR(); 152 bmips_init_cfe(); 153 bmips_cpu_setup(); 154 register_bmips_smp_ops(); 155 } 156 157 const char *get_system_type(void) 158 { 159 return "Generic BMIPS kernel"; 160 } 161 162 void __init plat_time_init(void) 163 { 164 struct device_node *np; 165 u32 freq; 166 167 np = of_find_node_by_name(NULL, "cpus"); 168 if (!np) 169 panic("missing 'cpus' DT node"); 170 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) 171 panic("missing 'mips-hpt-frequency' property"); 172 of_node_put(np); 173 174 mips_hpt_frequency = freq; 175 } 176 177 void __init plat_mem_setup(void) 178 { 179 void *dtb; 180 const struct bmips_quirk *q; 181 182 set_io_port_base(0); 183 ioport_resource.start = 0; 184 ioport_resource.end = ~0; 185 186 /* 187 * intended to somewhat resemble ARM; see 188 * Documentation/arch/arm/booting.rst 189 */ 190 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) 191 dtb = phys_to_virt(fw_arg2); 192 else 193 dtb = get_fdt(); 194 195 if (!dtb) 196 cfe_die("no dtb found"); 197 198 __dt_setup_arch(dtb); 199 200 for (q = bmips_quirk_list; q->quirk_fn; q++) { 201 if (of_flat_dt_is_compatible(of_get_flat_dt_root(), 202 q->compatible)) { 203 q->quirk_fn(); 204 } 205 } 206 } 207 208 void __init device_tree_init(void) 209 { 210 struct device_node *np; 211 212 unflatten_and_copy_device_tree(); 213 214 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ 215 np = of_find_node_by_name(NULL, "cpus"); 216 if (np && of_get_available_child_count(np) <= 1) 217 bmips_smp_enabled = 0; 218 of_node_put(np); 219 } 220 221 static int __init plat_dev_init(void) 222 { 223 of_clk_init(NULL); 224 return 0; 225 } 226 227 arch_initcall(plat_dev_init); 228