1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 */ 8 9 #include <linux/init.h> 10 #include <linux/memblock.h> 11 #include <linux/smp.h> 12 #include <asm/bootinfo.h> 13 #include <asm/bmips.h> 14 #include <asm/smp-ops.h> 15 #include <asm/mipsregs.h> 16 #include <bcm63xx_board.h> 17 #include <bcm63xx_cpu.h> 18 #include <bcm63xx_io.h> 19 #include <bcm63xx_regs.h> 20 21 void __init prom_init(void) 22 { 23 u32 reg, mask; 24 25 /* Cache CBR addr before CPU/DMA setup */ 26 bmips_cbr_addr = BMIPS_GET_CBR(); 27 28 bcm63xx_cpu_init(); 29 30 /* stop any running watchdog */ 31 bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG); 32 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); 33 34 /* disable all hardware blocks clock for now */ 35 if (BCMCPU_IS_3368()) 36 mask = CKCTL_3368_ALL_SAFE_EN; 37 else if (BCMCPU_IS_6328()) 38 mask = CKCTL_6328_ALL_SAFE_EN; 39 else if (BCMCPU_IS_6338()) 40 mask = CKCTL_6338_ALL_SAFE_EN; 41 else if (BCMCPU_IS_6345()) 42 mask = CKCTL_6345_ALL_SAFE_EN; 43 else if (BCMCPU_IS_6348()) 44 mask = CKCTL_6348_ALL_SAFE_EN; 45 else if (BCMCPU_IS_6358()) 46 mask = CKCTL_6358_ALL_SAFE_EN; 47 else if (BCMCPU_IS_6362()) 48 mask = CKCTL_6362_ALL_SAFE_EN; 49 else if (BCMCPU_IS_6368()) 50 mask = CKCTL_6368_ALL_SAFE_EN; 51 else 52 mask = 0; 53 54 reg = bcm_perf_readl(PERF_CKCTL_REG); 55 reg &= ~mask; 56 bcm_perf_writel(reg, PERF_CKCTL_REG); 57 58 /* do low level board init */ 59 board_prom_init(); 60 61 /* set up SMP */ 62 if (!register_bmips_smp_ops()) { 63 /* 64 * BCM6328 might not have its second CPU enabled, while BCM3368 65 * and BCM6358 need special handling for their shared TLB, so 66 * disable SMP for now. 67 */ 68 if (BCMCPU_IS_6328()) { 69 reg = bcm_readl(BCM_6328_OTP_BASE + 70 OTP_USER_BITS_6328_REG(3)); 71 72 if (reg & OTP_6328_REG3_TP1_DISABLED) 73 bmips_smp_enabled = 0; 74 } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { 75 bmips_smp_enabled = 0; 76 } 77 78 if (!bmips_smp_enabled) 79 return; 80 81 /* 82 * The bootloader has set up the CPU1 reset vector at 83 * 0xa000_0200. 84 * This conflicts with the special interrupt vector (IV). 85 * The bootloader has also set up CPU1 to respond to the wrong 86 * IPI interrupt. 87 * Here we will start up CPU1 in the background and ask it to 88 * reconfigure itself then go back to sleep. 89 */ 90 memcpy((void *)0xa0000200, bmips_smp_movevec, 0x20); 91 __sync(); 92 set_c0_cause(C_SW0); 93 cpumask_set_cpu(1, &bmips_booted_mask); 94 95 /* 96 * FIXME: we really should have some sort of hazard barrier here 97 */ 98 } 99 } 100