1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <bcm63xx_cpu.h> 15 #include <bcm63xx_regs.h> 16 #include <bcm63xx_io.h> 17 #include <bcm63xx_irq.h> 18 19 const unsigned long *bcm63xx_regs_base; 20 EXPORT_SYMBOL(bcm63xx_regs_base); 21 22 const int *bcm63xx_irqs; 23 EXPORT_SYMBOL(bcm63xx_irqs); 24 25 static u16 bcm63xx_cpu_id; 26 static u16 bcm63xx_cpu_rev; 27 static unsigned int bcm63xx_cpu_freq; 28 static unsigned int bcm63xx_memory_size; 29 30 /* 31 * 6338 register sets and irqs 32 */ 33 static const unsigned long bcm96338_regs_base[] = { 34 [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE, 35 [RSET_PERF] = BCM_6338_PERF_BASE, 36 [RSET_TIMER] = BCM_6338_TIMER_BASE, 37 [RSET_WDT] = BCM_6338_WDT_BASE, 38 [RSET_UART0] = BCM_6338_UART0_BASE, 39 [RSET_UART1] = BCM_6338_UART1_BASE, 40 [RSET_GPIO] = BCM_6338_GPIO_BASE, 41 [RSET_SPI] = BCM_6338_SPI_BASE, 42 [RSET_OHCI0] = BCM_6338_OHCI0_BASE, 43 [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE, 44 [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE, 45 [RSET_UDC0] = BCM_6338_UDC0_BASE, 46 [RSET_MPI] = BCM_6338_MPI_BASE, 47 [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE, 48 [RSET_SDRAM] = BCM_6338_SDRAM_BASE, 49 [RSET_DSL] = BCM_6338_DSL_BASE, 50 [RSET_ENET0] = BCM_6338_ENET0_BASE, 51 [RSET_ENET1] = BCM_6338_ENET1_BASE, 52 [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE, 53 [RSET_MEMC] = BCM_6338_MEMC_BASE, 54 [RSET_DDR] = BCM_6338_DDR_BASE, 55 }; 56 57 static const int bcm96338_irqs[] = { 58 [IRQ_TIMER] = BCM_6338_TIMER_IRQ, 59 [IRQ_UART0] = BCM_6338_UART0_IRQ, 60 [IRQ_DSL] = BCM_6338_DSL_IRQ, 61 [IRQ_ENET0] = BCM_6338_ENET0_IRQ, 62 [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ, 63 [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ, 64 [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ, 65 }; 66 67 /* 68 * 6345 register sets and irqs 69 */ 70 static const unsigned long bcm96345_regs_base[] = { 71 [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE, 72 [RSET_PERF] = BCM_6345_PERF_BASE, 73 [RSET_TIMER] = BCM_6345_TIMER_BASE, 74 [RSET_WDT] = BCM_6345_WDT_BASE, 75 [RSET_UART0] = BCM_6345_UART0_BASE, 76 [RSET_UART1] = BCM_6345_UART1_BASE, 77 [RSET_GPIO] = BCM_6345_GPIO_BASE, 78 [RSET_SPI] = BCM_6345_SPI_BASE, 79 [RSET_UDC0] = BCM_6345_UDC0_BASE, 80 [RSET_OHCI0] = BCM_6345_OHCI0_BASE, 81 [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE, 82 [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE, 83 [RSET_MPI] = BCM_6345_MPI_BASE, 84 [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE, 85 [RSET_DSL] = BCM_6345_DSL_BASE, 86 [RSET_ENET0] = BCM_6345_ENET0_BASE, 87 [RSET_ENET1] = BCM_6345_ENET1_BASE, 88 [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE, 89 [RSET_EHCI0] = BCM_6345_EHCI0_BASE, 90 [RSET_SDRAM] = BCM_6345_SDRAM_BASE, 91 [RSET_MEMC] = BCM_6345_MEMC_BASE, 92 [RSET_DDR] = BCM_6345_DDR_BASE, 93 }; 94 95 static const int bcm96345_irqs[] = { 96 [IRQ_TIMER] = BCM_6345_TIMER_IRQ, 97 [IRQ_UART0] = BCM_6345_UART0_IRQ, 98 [IRQ_DSL] = BCM_6345_DSL_IRQ, 99 [IRQ_ENET0] = BCM_6345_ENET0_IRQ, 100 [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ, 101 [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ, 102 [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ, 103 }; 104 105 /* 106 * 6348 register sets and irqs 107 */ 108 static const unsigned long bcm96348_regs_base[] = { 109 [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE, 110 [RSET_PERF] = BCM_6348_PERF_BASE, 111 [RSET_TIMER] = BCM_6348_TIMER_BASE, 112 [RSET_WDT] = BCM_6348_WDT_BASE, 113 [RSET_UART0] = BCM_6348_UART0_BASE, 114 [RSET_UART1] = BCM_6348_UART1_BASE, 115 [RSET_GPIO] = BCM_6348_GPIO_BASE, 116 [RSET_SPI] = BCM_6348_SPI_BASE, 117 [RSET_OHCI0] = BCM_6348_OHCI0_BASE, 118 [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE, 119 [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE, 120 [RSET_MPI] = BCM_6348_MPI_BASE, 121 [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE, 122 [RSET_SDRAM] = BCM_6348_SDRAM_BASE, 123 [RSET_DSL] = BCM_6348_DSL_BASE, 124 [RSET_ENET0] = BCM_6348_ENET0_BASE, 125 [RSET_ENET1] = BCM_6348_ENET1_BASE, 126 [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE, 127 [RSET_MEMC] = BCM_6348_MEMC_BASE, 128 [RSET_DDR] = BCM_6348_DDR_BASE, 129 }; 130 131 static const int bcm96348_irqs[] = { 132 [IRQ_TIMER] = BCM_6348_TIMER_IRQ, 133 [IRQ_UART0] = BCM_6348_UART0_IRQ, 134 [IRQ_DSL] = BCM_6348_DSL_IRQ, 135 [IRQ_ENET0] = BCM_6348_ENET0_IRQ, 136 [IRQ_ENET1] = BCM_6348_ENET1_IRQ, 137 [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ, 138 [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ, 139 [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ, 140 [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ, 141 [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ, 142 [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ, 143 [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ, 144 [IRQ_PCI] = BCM_6348_PCI_IRQ, 145 }; 146 147 /* 148 * 6358 register sets and irqs 149 */ 150 static const unsigned long bcm96358_regs_base[] = { 151 [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE, 152 [RSET_PERF] = BCM_6358_PERF_BASE, 153 [RSET_TIMER] = BCM_6358_TIMER_BASE, 154 [RSET_WDT] = BCM_6358_WDT_BASE, 155 [RSET_UART0] = BCM_6358_UART0_BASE, 156 [RSET_UART1] = BCM_6358_UART1_BASE, 157 [RSET_GPIO] = BCM_6358_GPIO_BASE, 158 [RSET_SPI] = BCM_6358_SPI_BASE, 159 [RSET_OHCI0] = BCM_6358_OHCI0_BASE, 160 [RSET_EHCI0] = BCM_6358_EHCI0_BASE, 161 [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE, 162 [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE, 163 [RSET_MPI] = BCM_6358_MPI_BASE, 164 [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE, 165 [RSET_SDRAM] = BCM_6358_SDRAM_BASE, 166 [RSET_DSL] = BCM_6358_DSL_BASE, 167 [RSET_ENET0] = BCM_6358_ENET0_BASE, 168 [RSET_ENET1] = BCM_6358_ENET1_BASE, 169 [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE, 170 [RSET_MEMC] = BCM_6358_MEMC_BASE, 171 [RSET_DDR] = BCM_6358_DDR_BASE, 172 }; 173 174 static const int bcm96358_irqs[] = { 175 [IRQ_TIMER] = BCM_6358_TIMER_IRQ, 176 [IRQ_UART0] = BCM_6358_UART0_IRQ, 177 [IRQ_UART1] = BCM_6358_UART1_IRQ, 178 [IRQ_DSL] = BCM_6358_DSL_IRQ, 179 [IRQ_ENET0] = BCM_6358_ENET0_IRQ, 180 [IRQ_ENET1] = BCM_6358_ENET1_IRQ, 181 [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ, 182 [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ, 183 [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ, 184 [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ, 185 [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ, 186 [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ, 187 [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ, 188 [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ, 189 [IRQ_PCI] = BCM_6358_PCI_IRQ, 190 }; 191 192 u16 __bcm63xx_get_cpu_id(void) 193 { 194 return bcm63xx_cpu_id; 195 } 196 197 EXPORT_SYMBOL(__bcm63xx_get_cpu_id); 198 199 u16 bcm63xx_get_cpu_rev(void) 200 { 201 return bcm63xx_cpu_rev; 202 } 203 204 EXPORT_SYMBOL(bcm63xx_get_cpu_rev); 205 206 unsigned int bcm63xx_get_cpu_freq(void) 207 { 208 return bcm63xx_cpu_freq; 209 } 210 211 unsigned int bcm63xx_get_memory_size(void) 212 { 213 return bcm63xx_memory_size; 214 } 215 216 static unsigned int detect_cpu_clock(void) 217 { 218 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0; 219 220 /* BCM6338 has a fixed 240 Mhz frequency */ 221 if (BCMCPU_IS_6338()) 222 return 240000000; 223 224 /* BCM6345 has a fixed 140Mhz frequency */ 225 if (BCMCPU_IS_6345()) 226 return 140000000; 227 228 /* 229 * frequency depends on PLL configuration: 230 */ 231 if (BCMCPU_IS_6348()) { 232 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ 233 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); 234 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; 235 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT; 236 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT; 237 n1 += 1; 238 n2 += 2; 239 m1 += 1; 240 } 241 242 if (BCMCPU_IS_6358()) { 243 /* 16MHz * N1 * N2 / M1_CPU */ 244 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); 245 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; 246 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; 247 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; 248 } 249 250 return (16 * 1000000 * n1 * n2) / m1; 251 } 252 253 /* 254 * attempt to detect the amount of memory installed 255 */ 256 static unsigned int detect_memory_size(void) 257 { 258 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; 259 u32 val; 260 261 if (BCMCPU_IS_6345()) 262 return (8 * 1024 * 1024); 263 264 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { 265 val = bcm_sdram_readl(SDRAM_CFG_REG); 266 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; 267 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; 268 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; 269 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 270 } 271 272 if (BCMCPU_IS_6358()) { 273 val = bcm_memc_readl(MEMC_CFG_REG); 274 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 275 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; 276 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1; 277 banks = 2; 278 } 279 280 /* 0 => 11 address bits ... 2 => 13 address bits */ 281 rows += 11; 282 283 /* 0 => 8 address bits ... 2 => 10 address bits */ 284 cols += 8; 285 286 return 1 << (cols + rows + (is_32bits + 1) + banks); 287 } 288 289 void __init bcm63xx_cpu_init(void) 290 { 291 unsigned int tmp, expected_cpu_id; 292 struct cpuinfo_mips *c = ¤t_cpu_data; 293 unsigned int cpu = smp_processor_id(); 294 295 /* soc registers location depends on cpu type */ 296 expected_cpu_id = 0; 297 298 switch (c->cputype) { 299 /* 300 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c 301 */ 302 case CPU_BCM3302: 303 __cpu_name[cpu] = "Broadcom BCM6338"; 304 expected_cpu_id = BCM6338_CPU_ID; 305 bcm63xx_regs_base = bcm96338_regs_base; 306 bcm63xx_irqs = bcm96338_irqs; 307 break; 308 case CPU_BCM6345: 309 expected_cpu_id = BCM6345_CPU_ID; 310 bcm63xx_regs_base = bcm96345_regs_base; 311 bcm63xx_irqs = bcm96345_irqs; 312 break; 313 case CPU_BCM6348: 314 expected_cpu_id = BCM6348_CPU_ID; 315 bcm63xx_regs_base = bcm96348_regs_base; 316 bcm63xx_irqs = bcm96348_irqs; 317 break; 318 case CPU_BCM6358: 319 expected_cpu_id = BCM6358_CPU_ID; 320 bcm63xx_regs_base = bcm96358_regs_base; 321 bcm63xx_irqs = bcm96358_irqs; 322 break; 323 } 324 325 /* 326 * really early to panic, but delaying panic would not help since we 327 * will never get any working console 328 */ 329 if (!expected_cpu_id) 330 panic("unsupported Broadcom CPU"); 331 332 /* 333 * bcm63xx_regs_base is set, we can access soc registers 334 */ 335 336 /* double check CPU type */ 337 tmp = bcm_perf_readl(PERF_REV_REG); 338 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; 339 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; 340 341 if (bcm63xx_cpu_id != expected_cpu_id) 342 panic("bcm63xx CPU id mismatch"); 343 344 bcm63xx_cpu_freq = detect_cpu_clock(); 345 bcm63xx_memory_size = detect_memory_size(); 346 347 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", 348 bcm63xx_cpu_id, bcm63xx_cpu_rev); 349 printk(KERN_INFO "CPU frequency is %u MHz\n", 350 bcm63xx_cpu_freq / 1000000); 351 printk(KERN_INFO "%uMB of RAM installed\n", 352 bcm63xx_memory_size >> 20); 353 } 354