1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atheros AR71XX/AR724X/AR913X specific setup 4 * 5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * 9 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/memblock.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/of_clk.h> 19 #include <linux/of_fdt.h> 20 #include <linux/irqchip.h> 21 22 #include <asm/bootinfo.h> 23 #include <asm/idle.h> 24 #include <asm/time.h> /* for mips_hpt_frequency */ 25 #include <asm/reboot.h> /* for _machine_{restart,halt} */ 26 #include <asm/prom.h> 27 #include <asm/fw/fw.h> 28 29 #include <asm/mach-ath79/ath79.h> 30 #include <asm/mach-ath79/ar71xx_regs.h> 31 #include "common.h" 32 33 #define ATH79_SYS_TYPE_LEN 64 34 35 static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; 36 37 static void ath79_halt(void) 38 { 39 while (1) 40 cpu_wait(); 41 } 42 43 static void __init ath79_detect_sys_type(void) 44 { 45 char *chip = "????"; 46 u32 id; 47 u32 major; 48 u32 minor; 49 u32 rev = 0; 50 u32 ver = 1; 51 52 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); 53 major = id & REV_ID_MAJOR_MASK; 54 55 switch (major) { 56 case REV_ID_MAJOR_AR71XX: 57 minor = id & AR71XX_REV_ID_MINOR_MASK; 58 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; 59 rev &= AR71XX_REV_ID_REVISION_MASK; 60 switch (minor) { 61 case AR71XX_REV_ID_MINOR_AR7130: 62 ath79_soc = ATH79_SOC_AR7130; 63 chip = "7130"; 64 break; 65 66 case AR71XX_REV_ID_MINOR_AR7141: 67 ath79_soc = ATH79_SOC_AR7141; 68 chip = "7141"; 69 break; 70 71 case AR71XX_REV_ID_MINOR_AR7161: 72 ath79_soc = ATH79_SOC_AR7161; 73 chip = "7161"; 74 break; 75 } 76 break; 77 78 case REV_ID_MAJOR_AR7240: 79 ath79_soc = ATH79_SOC_AR7240; 80 chip = "7240"; 81 rev = id & AR724X_REV_ID_REVISION_MASK; 82 break; 83 84 case REV_ID_MAJOR_AR7241: 85 ath79_soc = ATH79_SOC_AR7241; 86 chip = "7241"; 87 rev = id & AR724X_REV_ID_REVISION_MASK; 88 break; 89 90 case REV_ID_MAJOR_AR7242: 91 ath79_soc = ATH79_SOC_AR7242; 92 chip = "7242"; 93 rev = id & AR724X_REV_ID_REVISION_MASK; 94 break; 95 96 case REV_ID_MAJOR_AR913X: 97 minor = id & AR913X_REV_ID_MINOR_MASK; 98 rev = id >> AR913X_REV_ID_REVISION_SHIFT; 99 rev &= AR913X_REV_ID_REVISION_MASK; 100 switch (minor) { 101 case AR913X_REV_ID_MINOR_AR9130: 102 ath79_soc = ATH79_SOC_AR9130; 103 chip = "9130"; 104 break; 105 106 case AR913X_REV_ID_MINOR_AR9132: 107 ath79_soc = ATH79_SOC_AR9132; 108 chip = "9132"; 109 break; 110 } 111 break; 112 113 case REV_ID_MAJOR_AR9330: 114 ath79_soc = ATH79_SOC_AR9330; 115 chip = "9330"; 116 rev = id & AR933X_REV_ID_REVISION_MASK; 117 break; 118 119 case REV_ID_MAJOR_AR9331: 120 ath79_soc = ATH79_SOC_AR9331; 121 chip = "9331"; 122 rev = id & AR933X_REV_ID_REVISION_MASK; 123 break; 124 125 case REV_ID_MAJOR_AR9341: 126 ath79_soc = ATH79_SOC_AR9341; 127 chip = "9341"; 128 rev = id & AR934X_REV_ID_REVISION_MASK; 129 break; 130 131 case REV_ID_MAJOR_AR9342: 132 ath79_soc = ATH79_SOC_AR9342; 133 chip = "9342"; 134 rev = id & AR934X_REV_ID_REVISION_MASK; 135 break; 136 137 case REV_ID_MAJOR_AR9344: 138 ath79_soc = ATH79_SOC_AR9344; 139 chip = "9344"; 140 rev = id & AR934X_REV_ID_REVISION_MASK; 141 break; 142 143 case REV_ID_MAJOR_QCA9533_V2: 144 ver = 2; 145 ath79_soc_rev = 2; 146 fallthrough; 147 case REV_ID_MAJOR_QCA9533: 148 ath79_soc = ATH79_SOC_QCA9533; 149 chip = "9533"; 150 rev = id & QCA953X_REV_ID_REVISION_MASK; 151 break; 152 153 case REV_ID_MAJOR_QCA9556: 154 ath79_soc = ATH79_SOC_QCA9556; 155 chip = "9556"; 156 rev = id & QCA955X_REV_ID_REVISION_MASK; 157 break; 158 159 case REV_ID_MAJOR_QCA9558: 160 ath79_soc = ATH79_SOC_QCA9558; 161 chip = "9558"; 162 rev = id & QCA955X_REV_ID_REVISION_MASK; 163 break; 164 165 case REV_ID_MAJOR_QCA956X: 166 ath79_soc = ATH79_SOC_QCA956X; 167 chip = "956X"; 168 rev = id & QCA956X_REV_ID_REVISION_MASK; 169 break; 170 171 case REV_ID_MAJOR_QCN550X: 172 ath79_soc = ATH79_SOC_QCA956X; 173 chip = "550X"; 174 rev = id & QCA956X_REV_ID_REVISION_MASK; 175 break; 176 177 case REV_ID_MAJOR_TP9343: 178 ath79_soc = ATH79_SOC_TP9343; 179 chip = "9343"; 180 rev = id & QCA956X_REV_ID_REVISION_MASK; 181 break; 182 183 default: 184 panic("ath79: unknown SoC, id:0x%08x", id); 185 } 186 187 if (ver == 1) 188 ath79_soc_rev = rev; 189 190 if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x()) 191 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", 192 chip, ver, rev); 193 else if (soc_is_tp9343()) 194 sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", 195 chip, rev); 196 else 197 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 198 pr_info("SoC: %s\n", ath79_sys_type); 199 } 200 201 const char *get_system_type(void) 202 { 203 return ath79_sys_type; 204 } 205 206 unsigned int get_c0_compare_int(void) 207 { 208 return CP0_LEGACY_COMPARE_IRQ; 209 } 210 211 void __init plat_mem_setup(void) 212 { 213 void *dtb; 214 215 set_io_port_base(KSEG1); 216 217 /* Get the position of the FDT passed by the bootloader */ 218 dtb = (void *)fw_getenvl("fdt_start"); 219 if (dtb == NULL) 220 dtb = get_fdt(); 221 222 if (dtb) 223 __dt_setup_arch((void *)KSEG0ADDR(dtb)); 224 225 ath79_reset_base = ioremap(AR71XX_RESET_BASE, 226 AR71XX_RESET_SIZE); 227 ath79_pll_base = ioremap(AR71XX_PLL_BASE, 228 AR71XX_PLL_SIZE); 229 ath79_detect_sys_type(); 230 ath79_ddr_ctrl_init(); 231 232 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); 233 234 _machine_halt = ath79_halt; 235 pm_power_off = ath79_halt; 236 } 237 238 void __init plat_time_init(void) 239 { 240 struct device_node *np; 241 struct clk *clk; 242 unsigned long cpu_clk_rate; 243 244 of_clk_init(NULL); 245 246 np = of_get_cpu_node(0, NULL); 247 if (!np) { 248 pr_err("Failed to get CPU node\n"); 249 return; 250 } 251 252 clk = of_clk_get(np, 0); 253 if (IS_ERR(clk)) { 254 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); 255 return; 256 } 257 258 cpu_clk_rate = clk_get_rate(clk); 259 260 pr_info("CPU clock: %lu.%03lu MHz\n", 261 cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000); 262 263 mips_hpt_frequency = cpu_clk_rate / 2; 264 265 clk_put(clk); 266 } 267 268 void __init arch_init_irq(void) 269 { 270 irqchip_init(); 271 } 272