1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atheros AR71XX/AR724X/AR913X common routines 4 * 5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * 9 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/export.h> 14 #include <linux/types.h> 15 #include <linux/spinlock.h> 16 17 #include <asm/mach-ath79/ath79.h> 18 #include <asm/mach-ath79/ar71xx_regs.h> 19 #include "common.h" 20 21 static DEFINE_SPINLOCK(ath79_device_reset_lock); 22 23 u32 ath79_cpu_freq; 24 EXPORT_SYMBOL_GPL(ath79_cpu_freq); 25 26 u32 ath79_ahb_freq; 27 EXPORT_SYMBOL_GPL(ath79_ahb_freq); 28 29 u32 ath79_ddr_freq; 30 EXPORT_SYMBOL_GPL(ath79_ddr_freq); 31 32 enum ath79_soc_type ath79_soc; 33 unsigned int ath79_soc_rev; 34 35 void __iomem *ath79_pll_base; 36 void __iomem *ath79_reset_base; 37 EXPORT_SYMBOL_GPL(ath79_reset_base); 38 static void __iomem *ath79_ddr_base; 39 static void __iomem *ath79_ddr_wb_flush_base; 40 static void __iomem *ath79_ddr_pci_win_base; 41 42 void ath79_ddr_ctrl_init(void) 43 { 44 ath79_ddr_base = ioremap(AR71XX_DDR_CTRL_BASE, 45 AR71XX_DDR_CTRL_SIZE); 46 if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) { 47 ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c; 48 ath79_ddr_pci_win_base = 0; 49 } else { 50 ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; 51 ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; 52 } 53 } 54 EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); 55 56 void ath79_ddr_wb_flush(u32 reg) 57 { 58 void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4); 59 60 /* Flush the DDR write buffer. */ 61 __raw_writel(0x1, flush_reg); 62 while (__raw_readl(flush_reg) & 0x1) 63 ; 64 65 /* It must be run twice. */ 66 __raw_writel(0x1, flush_reg); 67 while (__raw_readl(flush_reg) & 0x1) 68 ; 69 } 70 EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush); 71 72 void ath79_ddr_set_pci_windows(void) 73 { 74 BUG_ON(!ath79_ddr_pci_win_base); 75 76 __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); 77 __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); 78 __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); 79 __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); 80 __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); 81 __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); 82 __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); 83 __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); 84 } 85 EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows); 86 87 void ath79_device_reset_set(u32 mask) 88 { 89 unsigned long flags; 90 u32 reg; 91 u32 t; 92 93 if (soc_is_ar71xx()) 94 reg = AR71XX_RESET_REG_RESET_MODULE; 95 else if (soc_is_ar724x()) 96 reg = AR724X_RESET_REG_RESET_MODULE; 97 else if (soc_is_ar913x()) 98 reg = AR913X_RESET_REG_RESET_MODULE; 99 else if (soc_is_ar933x()) 100 reg = AR933X_RESET_REG_RESET_MODULE; 101 else if (soc_is_ar934x()) 102 reg = AR934X_RESET_REG_RESET_MODULE; 103 else if (soc_is_qca953x()) 104 reg = QCA953X_RESET_REG_RESET_MODULE; 105 else if (soc_is_qca955x()) 106 reg = QCA955X_RESET_REG_RESET_MODULE; 107 else if (soc_is_qca956x() || soc_is_tp9343()) 108 reg = QCA956X_RESET_REG_RESET_MODULE; 109 else 110 BUG(); 111 112 spin_lock_irqsave(&ath79_device_reset_lock, flags); 113 t = ath79_reset_rr(reg); 114 ath79_reset_wr(reg, t | mask); 115 spin_unlock_irqrestore(&ath79_device_reset_lock, flags); 116 } 117 EXPORT_SYMBOL_GPL(ath79_device_reset_set); 118 119 void ath79_device_reset_clear(u32 mask) 120 { 121 unsigned long flags; 122 u32 reg; 123 u32 t; 124 125 if (soc_is_ar71xx()) 126 reg = AR71XX_RESET_REG_RESET_MODULE; 127 else if (soc_is_ar724x()) 128 reg = AR724X_RESET_REG_RESET_MODULE; 129 else if (soc_is_ar913x()) 130 reg = AR913X_RESET_REG_RESET_MODULE; 131 else if (soc_is_ar933x()) 132 reg = AR933X_RESET_REG_RESET_MODULE; 133 else if (soc_is_ar934x()) 134 reg = AR934X_RESET_REG_RESET_MODULE; 135 else if (soc_is_qca953x()) 136 reg = QCA953X_RESET_REG_RESET_MODULE; 137 else if (soc_is_qca955x()) 138 reg = QCA955X_RESET_REG_RESET_MODULE; 139 else if (soc_is_qca956x() || soc_is_tp9343()) 140 reg = QCA956X_RESET_REG_RESET_MODULE; 141 else 142 BUG(); 143 144 spin_lock_irqsave(&ath79_device_reset_lock, flags); 145 t = ath79_reset_rr(reg); 146 ath79_reset_wr(reg, t & ~mask); 147 spin_unlock_irqrestore(&ath79_device_reset_lock, flags); 148 } 149 EXPORT_SYMBOL_GPL(ath79_device_reset_clear); 150