1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Alchemy Db1550/Pb1550 board support 4 * 5 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/gpio.h> 11 #include <linux/i2c.h> 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/platnand.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/spi/spi.h> 20 #include <linux/spi/flash.h> 21 #include <asm/bootinfo.h> 22 #include <asm/mach-au1x00/au1000.h> 23 #include <asm/mach-au1x00/gpio-au1000.h> 24 #include <asm/mach-au1x00/au1xxx_eth.h> 25 #include <asm/mach-au1x00/au1xxx_dbdma.h> 26 #include <asm/mach-au1x00/au1xxx_psc.h> 27 #include <asm/mach-au1x00/au1550_spi.h> 28 #include <asm/mach-au1x00/au1550nd.h> 29 #include <asm/mach-db1x00/bcsr.h> 30 #include <prom.h> 31 32 #include "db1xxx.h" 33 #include "platform.h" 34 35 static void __init db1550_hw_setup(void) 36 { 37 void __iomem *base; 38 unsigned long v; 39 40 /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line) 41 * as well as PSC1_SYNC for AC97 on PB1550. 42 */ 43 v = alchemy_rdsys(AU1000_SYS_PINFUNC); 44 alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC); 45 46 /* reset the AC97 codec now, the reset time in the psc-ac97 driver 47 * is apparently too short although it's ridiculous as it is. 48 */ 49 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR); 50 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE, 51 base + PSC_SEL_OFFSET); 52 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET); 53 wmb(); 54 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); 55 wmb(); 56 } 57 58 int __init db1550_board_setup(void) 59 { 60 unsigned short whoami; 61 62 bcsr_init(DB1550_BCSR_PHYS_ADDR, 63 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS); 64 65 whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */ 66 switch (BCSR_WHOAMI_BOARD(whoami)) { 67 case BCSR_WHOAMI_PB1550_SDR: 68 case BCSR_WHOAMI_PB1550_DDR: 69 bcsr_init(PB1550_BCSR_PHYS_ADDR, 70 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); 71 break; 72 case BCSR_WHOAMI_DB1550: 73 break; 74 default: 75 return -ENODEV; 76 } 77 78 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \ 79 "Daughtercard ID %d\n", get_system_type(), 80 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 81 82 db1550_hw_setup(); 83 return 0; 84 } 85 86 /*****************************************************************************/ 87 88 static u64 au1550_all_dmamask = DMA_BIT_MASK(32); 89 90 static struct mtd_partition db1550_spiflash_parts[] = { 91 { 92 .name = "spi_flash", 93 .offset = 0, 94 .size = MTDPART_SIZ_FULL, 95 }, 96 }; 97 98 static struct flash_platform_data db1550_spiflash_data = { 99 .name = "s25fl010", 100 .parts = db1550_spiflash_parts, 101 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts), 102 .type = "m25p10", 103 }; 104 105 static struct spi_board_info db1550_spi_devs[] __initdata = { 106 { 107 /* TI TMP121AIDBVR temp sensor */ 108 .modalias = "tmp121", 109 .max_speed_hz = 2400000, 110 .bus_num = 0, 111 .chip_select = 0, 112 .mode = SPI_MODE_0, 113 }, 114 { 115 /* Spansion S25FL001D0FMA SPI flash */ 116 .modalias = "m25p80", 117 .max_speed_hz = 2400000, 118 .bus_num = 0, 119 .chip_select = 1, 120 .mode = SPI_MODE_0, 121 .platform_data = &db1550_spiflash_data, 122 }, 123 }; 124 125 static struct i2c_board_info db1550_i2c_devs[] __initdata = { 126 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */ 127 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */ 128 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */ 129 }; 130 131 /**********************************************************************/ 132 133 static void au1550_nand_cmd_ctrl(struct nand_chip *this, int cmd, 134 unsigned int ctrl) 135 { 136 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W; 137 138 ioaddr &= 0xffffff00; 139 140 if (ctrl & NAND_CLE) { 141 ioaddr += MEM_STNAND_CMD; 142 } else if (ctrl & NAND_ALE) { 143 ioaddr += MEM_STNAND_ADDR; 144 } else { 145 /* assume we want to r/w real data by default */ 146 ioaddr += MEM_STNAND_DATA; 147 } 148 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr; 149 if (cmd != NAND_CMD_NONE) { 150 __raw_writeb(cmd, this->legacy.IO_ADDR_W); 151 wmb(); 152 } 153 } 154 155 static int au1550_nand_device_ready(struct nand_chip *this) 156 { 157 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 158 } 159 160 static struct mtd_partition db1550_nand_parts[] = { 161 { 162 .name = "NAND FS 0", 163 .offset = 0, 164 .size = 8 * 1024 * 1024, 165 }, 166 { 167 .name = "NAND FS 1", 168 .offset = MTDPART_OFS_APPEND, 169 .size = MTDPART_SIZ_FULL 170 }, 171 }; 172 173 struct platform_nand_data db1550_nand_platdata = { 174 .chip = { 175 .nr_chips = 1, 176 .chip_offset = 0, 177 .nr_partitions = ARRAY_SIZE(db1550_nand_parts), 178 .partitions = db1550_nand_parts, 179 .chip_delay = 20, 180 }, 181 .ctrl = { 182 .dev_ready = au1550_nand_device_ready, 183 .cmd_ctrl = au1550_nand_cmd_ctrl, 184 }, 185 }; 186 187 static struct resource db1550_nand_res[] = { 188 [0] = { 189 .start = 0x20000000, 190 .end = 0x200000ff, 191 .flags = IORESOURCE_MEM, 192 }, 193 }; 194 195 static struct platform_device db1550_nand_dev = { 196 .name = "gen_nand", 197 .num_resources = ARRAY_SIZE(db1550_nand_res), 198 .resource = db1550_nand_res, 199 .id = -1, 200 .dev = { 201 .platform_data = &db1550_nand_platdata, 202 } 203 }; 204 205 static struct au1550nd_platdata pb1550_nand_pd = { 206 .parts = db1550_nand_parts, 207 .num_parts = ARRAY_SIZE(db1550_nand_parts), 208 .devwidth = 0, /* x8 NAND default, needs fixing up */ 209 }; 210 211 static struct platform_device pb1550_nand_dev = { 212 .name = "au1550-nand", 213 .id = -1, 214 .resource = db1550_nand_res, 215 .num_resources = ARRAY_SIZE(db1550_nand_res), 216 .dev = { 217 .platform_data = &pb1550_nand_pd, 218 }, 219 }; 220 221 static void __init pb1550_nand_setup(void) 222 { 223 int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) | 224 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); 225 226 gpio_direction_input(206); /* de-assert NAND CS# */ 227 switch (boot_swapboot) { 228 case 0: case 2: case 8: case 0xC: case 0xD: 229 /* x16 NAND Flash */ 230 pb1550_nand_pd.devwidth = 1; 231 fallthrough; 232 case 1: case 3: case 9: case 0xE: case 0xF: 233 /* x8 NAND, already set up */ 234 platform_device_register(&pb1550_nand_dev); 235 } 236 } 237 238 /**********************************************************************/ 239 240 static struct resource au1550_psc0_res[] = { 241 [0] = { 242 .start = AU1550_PSC0_PHYS_ADDR, 243 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 244 .flags = IORESOURCE_MEM, 245 }, 246 [1] = { 247 .start = AU1550_PSC0_INT, 248 .end = AU1550_PSC0_INT, 249 .flags = IORESOURCE_IRQ, 250 }, 251 [2] = { 252 .start = AU1550_DSCR_CMD0_PSC0_TX, 253 .end = AU1550_DSCR_CMD0_PSC0_TX, 254 .flags = IORESOURCE_DMA, 255 }, 256 [3] = { 257 .start = AU1550_DSCR_CMD0_PSC0_RX, 258 .end = AU1550_DSCR_CMD0_PSC0_RX, 259 .flags = IORESOURCE_DMA, 260 }, 261 }; 262 263 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 264 { 265 if (cs) 266 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL); 267 else 268 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0); 269 } 270 271 static struct au1550_spi_info db1550_spi_platdata = { 272 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */ 273 .num_chipselect = 2, 274 .activate_cs = db1550_spi_cs_en, 275 }; 276 277 278 static struct platform_device db1550_spi_dev = { 279 .dev = { 280 .dma_mask = &au1550_all_dmamask, 281 .coherent_dma_mask = DMA_BIT_MASK(32), 282 .platform_data = &db1550_spi_platdata, 283 }, 284 .name = "au1550-spi", 285 .id = 0, /* bus number */ 286 .num_resources = ARRAY_SIZE(au1550_psc0_res), 287 .resource = au1550_psc0_res, 288 }; 289 290 /**********************************************************************/ 291 292 static struct resource au1550_psc1_res[] = { 293 [0] = { 294 .start = AU1550_PSC1_PHYS_ADDR, 295 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 296 .flags = IORESOURCE_MEM, 297 }, 298 [1] = { 299 .start = AU1550_PSC1_INT, 300 .end = AU1550_PSC1_INT, 301 .flags = IORESOURCE_IRQ, 302 }, 303 [2] = { 304 .start = AU1550_DSCR_CMD0_PSC1_TX, 305 .end = AU1550_DSCR_CMD0_PSC1_TX, 306 .flags = IORESOURCE_DMA, 307 }, 308 [3] = { 309 .start = AU1550_DSCR_CMD0_PSC1_RX, 310 .end = AU1550_DSCR_CMD0_PSC1_RX, 311 .flags = IORESOURCE_DMA, 312 }, 313 }; 314 315 static struct platform_device db1550_ac97_dev = { 316 .name = "au1xpsc_ac97", 317 .id = 1, /* PSC ID */ 318 .num_resources = ARRAY_SIZE(au1550_psc1_res), 319 .resource = au1550_psc1_res, 320 }; 321 322 323 static struct resource au1550_psc2_res[] = { 324 [0] = { 325 .start = AU1550_PSC2_PHYS_ADDR, 326 .end = AU1550_PSC2_PHYS_ADDR + 0xfff, 327 .flags = IORESOURCE_MEM, 328 }, 329 [1] = { 330 .start = AU1550_PSC2_INT, 331 .end = AU1550_PSC2_INT, 332 .flags = IORESOURCE_IRQ, 333 }, 334 [2] = { 335 .start = AU1550_DSCR_CMD0_PSC2_TX, 336 .end = AU1550_DSCR_CMD0_PSC2_TX, 337 .flags = IORESOURCE_DMA, 338 }, 339 [3] = { 340 .start = AU1550_DSCR_CMD0_PSC2_RX, 341 .end = AU1550_DSCR_CMD0_PSC2_RX, 342 .flags = IORESOURCE_DMA, 343 }, 344 }; 345 346 static struct platform_device db1550_i2c_dev = { 347 .name = "au1xpsc_smbus", 348 .id = 0, /* bus number */ 349 .num_resources = ARRAY_SIZE(au1550_psc2_res), 350 .resource = au1550_psc2_res, 351 }; 352 353 /**********************************************************************/ 354 355 static struct resource au1550_psc3_res[] = { 356 [0] = { 357 .start = AU1550_PSC3_PHYS_ADDR, 358 .end = AU1550_PSC3_PHYS_ADDR + 0xfff, 359 .flags = IORESOURCE_MEM, 360 }, 361 [1] = { 362 .start = AU1550_PSC3_INT, 363 .end = AU1550_PSC3_INT, 364 .flags = IORESOURCE_IRQ, 365 }, 366 [2] = { 367 .start = AU1550_DSCR_CMD0_PSC3_TX, 368 .end = AU1550_DSCR_CMD0_PSC3_TX, 369 .flags = IORESOURCE_DMA, 370 }, 371 [3] = { 372 .start = AU1550_DSCR_CMD0_PSC3_RX, 373 .end = AU1550_DSCR_CMD0_PSC3_RX, 374 .flags = IORESOURCE_DMA, 375 }, 376 }; 377 378 static struct platform_device db1550_i2s_dev = { 379 .name = "au1xpsc_i2s", 380 .id = 3, /* PSC ID */ 381 .num_resources = ARRAY_SIZE(au1550_psc3_res), 382 .resource = au1550_psc3_res, 383 }; 384 385 /**********************************************************************/ 386 387 static struct platform_device db1550_stac_dev = { 388 .name = "ac97-codec", 389 .id = 1, /* on PSC1 */ 390 }; 391 392 static struct platform_device db1550_ac97dma_dev = { 393 .name = "au1xpsc-pcm", 394 .id = 1, /* on PSC3 */ 395 }; 396 397 static struct platform_device db1550_i2sdma_dev = { 398 .name = "au1xpsc-pcm", 399 .id = 3, /* on PSC3 */ 400 }; 401 402 static struct platform_device db1550_sndac97_dev = { 403 .name = "db1550-ac97", 404 .dev = { 405 .dma_mask = &au1550_all_dmamask, 406 .coherent_dma_mask = DMA_BIT_MASK(32), 407 }, 408 }; 409 410 static struct platform_device db1550_sndi2s_dev = { 411 .name = "db1550-i2s", 412 .dev = { 413 .dma_mask = &au1550_all_dmamask, 414 .coherent_dma_mask = DMA_BIT_MASK(32), 415 }, 416 }; 417 418 /**********************************************************************/ 419 420 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) 421 { 422 if ((slot < 11) || (slot > 13) || pin == 0) 423 return -1; 424 if (slot == 11) 425 return (pin == 1) ? AU1550_PCI_INTC : 0xff; 426 if (slot == 12) { 427 switch (pin) { 428 case 1: return AU1550_PCI_INTB; 429 case 2: return AU1550_PCI_INTC; 430 case 3: return AU1550_PCI_INTD; 431 case 4: return AU1550_PCI_INTA; 432 } 433 } 434 if (slot == 13) { 435 switch (pin) { 436 case 1: return AU1550_PCI_INTA; 437 case 2: return AU1550_PCI_INTB; 438 case 3: return AU1550_PCI_INTC; 439 case 4: return AU1550_PCI_INTD; 440 } 441 } 442 return -1; 443 } 444 445 static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) 446 { 447 if ((slot < 12) || (slot > 13) || pin == 0) 448 return -1; 449 if (slot == 12) { 450 switch (pin) { 451 case 1: return AU1500_PCI_INTB; 452 case 2: return AU1500_PCI_INTC; 453 case 3: return AU1500_PCI_INTD; 454 case 4: return AU1500_PCI_INTA; 455 } 456 } 457 if (slot == 13) { 458 switch (pin) { 459 case 1: return AU1500_PCI_INTA; 460 case 2: return AU1500_PCI_INTB; 461 case 3: return AU1500_PCI_INTC; 462 case 4: return AU1500_PCI_INTD; 463 } 464 } 465 return -1; 466 } 467 468 static struct resource alchemy_pci_host_res[] = { 469 [0] = { 470 .start = AU1500_PCI_PHYS_ADDR, 471 .end = AU1500_PCI_PHYS_ADDR + 0xfff, 472 .flags = IORESOURCE_MEM, 473 }, 474 }; 475 476 static struct alchemy_pci_platdata db1550_pci_pd = { 477 .board_map_irq = db1550_map_pci_irq, 478 }; 479 480 static struct platform_device db1550_pci_host_dev = { 481 .dev.platform_data = &db1550_pci_pd, 482 .name = "alchemy-pci", 483 .id = 0, 484 .num_resources = ARRAY_SIZE(alchemy_pci_host_res), 485 .resource = alchemy_pci_host_res, 486 }; 487 488 /**********************************************************************/ 489 490 static struct platform_device *db1550_devs[] __initdata = { 491 &db1550_i2c_dev, 492 &db1550_ac97_dev, 493 &db1550_spi_dev, 494 &db1550_i2s_dev, 495 &db1550_stac_dev, 496 &db1550_ac97dma_dev, 497 &db1550_i2sdma_dev, 498 &db1550_sndac97_dev, 499 &db1550_sndi2s_dev, 500 }; 501 502 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ 503 int __init db1550_pci_setup(int id) 504 { 505 if (id) 506 db1550_pci_pd.board_map_irq = pb1550_map_pci_irq; 507 return platform_device_register(&db1550_pci_host_dev); 508 } 509 510 static void __init db1550_devices(void) 511 { 512 alchemy_gpio_direction_output(203, 0); /* red led on */ 513 514 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ 515 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ 516 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */ 517 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */ 518 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ 519 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ 520 521 db1x_register_pcmcia_socket( 522 AU1000_PCMCIA_ATTR_PHYS_ADDR, 523 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 524 AU1000_PCMCIA_MEM_PHYS_ADDR, 525 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 526 AU1000_PCMCIA_IO_PHYS_ADDR, 527 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 528 AU1550_GPIO3_INT, 0, 529 /*AU1550_GPIO21_INT*/0, 0, 0); 530 531 db1x_register_pcmcia_socket( 532 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 533 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 534 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 535 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 536 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 537 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 538 AU1550_GPIO5_INT, 1, 539 /*AU1550_GPIO22_INT*/0, 0, 1); 540 541 platform_device_register(&db1550_nand_dev); 542 543 alchemy_gpio_direction_output(202, 0); /* green led on */ 544 } 545 546 static void __init pb1550_devices(void) 547 { 548 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW); 549 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW); 550 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH); 551 552 /* enable both PCMCIA card irqs in the shared line */ 553 alchemy_gpio2_enable_int(201); /* socket 0 card irq */ 554 alchemy_gpio2_enable_int(202); /* socket 1 card irq */ 555 556 /* Pb1550, like all others, also has statuschange irqs; however they're 557 * wired up on one of the Au1550's shared GPIO201_205 line, which also 558 * services the PCMCIA card interrupts. So we ignore statuschange and 559 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia 560 * drivers are used to shared irqs and b) statuschange isn't really use- 561 * ful anyway. 562 */ 563 db1x_register_pcmcia_socket( 564 AU1000_PCMCIA_ATTR_PHYS_ADDR, 565 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 566 AU1000_PCMCIA_MEM_PHYS_ADDR, 567 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 568 AU1000_PCMCIA_IO_PHYS_ADDR, 569 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 570 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0); 571 572 db1x_register_pcmcia_socket( 573 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, 574 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, 575 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, 576 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, 577 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, 578 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, 579 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); 580 581 pb1550_nand_setup(); 582 } 583 584 int __init db1550_dev_setup(void) 585 { 586 int swapped, id; 587 struct clk *c; 588 589 id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550); 590 591 i2c_register_board_info(0, db1550_i2c_devs, 592 ARRAY_SIZE(db1550_i2c_devs)); 593 spi_register_board_info(db1550_spi_devs, 594 ARRAY_SIZE(db1550_spi_devs)); 595 596 c = clk_get(NULL, "psc0_intclk"); 597 if (!IS_ERR(c)) { 598 clk_set_rate(c, 50000000); 599 clk_prepare_enable(c); 600 clk_put(c); 601 } 602 c = clk_get(NULL, "psc2_intclk"); 603 if (!IS_ERR(c)) { 604 clk_set_rate(c, db1550_spi_platdata.mainclk_hz); 605 clk_prepare_enable(c); 606 clk_put(c); 607 } 608 609 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */ 610 __raw_writel(PSC_SEL_CLK_SERCLK, 611 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 612 wmb(); 613 __raw_writel(PSC_SEL_CLK_SERCLK, 614 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); 615 wmb(); 616 /* SPI/I2C use internally supplied 50MHz source */ 617 __raw_writel(PSC_SEL_CLK_INTCLK, 618 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET); 619 wmb(); 620 __raw_writel(PSC_SEL_CLK_INTCLK, 621 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); 622 wmb(); 623 624 id ? pb1550_devices() : db1550_devices(); 625 626 swapped = bcsr_read(BCSR_STATUS) & 627 (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT); 628 db1x_register_norflash(128 << 20, 4, swapped); 629 630 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); 631 } 632