1 /* 2 * DBAu1200/PBAu1200 board platform device registration 3 * 4 * Copyright (C) 2008-2011 Manuel Lauss 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 #include <linux/dma-mapping.h> 22 #include <linux/gpio.h> 23 #include <linux/i2c.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/leds.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mtd/mtd.h> 30 #include <linux/mtd/nand.h> 31 #include <linux/mtd/partitions.h> 32 #include <linux/platform_device.h> 33 #include <linux/serial_8250.h> 34 #include <linux/spi/spi.h> 35 #include <linux/spi/flash.h> 36 #include <linux/smc91x.h> 37 #include <asm/mach-au1x00/au1000.h> 38 #include <asm/mach-au1x00/au1100_mmc.h> 39 #include <asm/mach-au1x00/au1xxx_dbdma.h> 40 #include <asm/mach-au1x00/au1200fb.h> 41 #include <asm/mach-au1x00/au1550_spi.h> 42 #include <asm/mach-db1x00/bcsr.h> 43 #include <asm/mach-db1x00/db1200.h> 44 45 #include "platform.h" 46 47 static const char *board_type_str(void) 48 { 49 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { 50 case BCSR_WHOAMI_PB1200_DDR1: 51 case BCSR_WHOAMI_PB1200_DDR2: 52 return "PB1200"; 53 case BCSR_WHOAMI_DB1200: 54 return "DB1200"; 55 default: 56 return "(unknown)"; 57 } 58 } 59 60 const char *get_system_type(void) 61 { 62 return board_type_str(); 63 } 64 65 static int __init detect_board(void) 66 { 67 int bid; 68 69 /* try the DB1200 first */ 70 bcsr_init(DB1200_BCSR_PHYS_ADDR, 71 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); 72 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { 73 unsigned short t = bcsr_read(BCSR_HEXLEDS); 74 bcsr_write(BCSR_HEXLEDS, ~t); 75 if (bcsr_read(BCSR_HEXLEDS) != t) { 76 bcsr_write(BCSR_HEXLEDS, t); 77 return 0; 78 } 79 } 80 81 /* okay, try the PB1200 then */ 82 bcsr_init(PB1200_BCSR_PHYS_ADDR, 83 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); 84 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 85 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 86 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 87 unsigned short t = bcsr_read(BCSR_HEXLEDS); 88 bcsr_write(BCSR_HEXLEDS, ~t); 89 if (bcsr_read(BCSR_HEXLEDS) != t) { 90 bcsr_write(BCSR_HEXLEDS, t); 91 return 0; 92 } 93 } 94 95 return 1; /* it's neither */ 96 } 97 98 void __init board_setup(void) 99 { 100 unsigned long freq0, clksrc, div, pfc; 101 unsigned short whoami; 102 103 if (detect_board()) { 104 printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n"); 105 return; 106 } 107 108 whoami = bcsr_read(BCSR_WHOAMI); 109 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" 110 " Board-ID %d Daughtercard ID %d\n", board_type_str(), 111 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 112 113 /* SMBus/SPI on PSC0, Audio on PSC1 */ 114 pfc = __raw_readl((void __iomem *)SYS_PINFUNC); 115 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); 116 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); 117 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ 118 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); 119 wmb(); 120 121 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from 122 * CPU clock; all other clock generators off/unused. 123 */ 124 div = (get_au1x00_speed() + 25000000) / 50000000; 125 if (div & 1) 126 div++; 127 div = ((div >> 1) - 1) & 0xff; 128 129 freq0 = div << SYS_FC_FRDIV0_BIT; 130 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); 131 wmb(); 132 freq0 |= SYS_FC_FE0; /* enable F0 */ 133 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); 134 wmb(); 135 136 /* psc0_intclk comes 1:1 from F0 */ 137 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; 138 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); 139 wmb(); 140 } 141 142 /******************************************************************************/ 143 144 static struct mtd_partition db1200_spiflash_parts[] = { 145 { 146 .name = "spi_flash", 147 .offset = 0, 148 .size = MTDPART_SIZ_FULL, 149 }, 150 }; 151 152 static struct flash_platform_data db1200_spiflash_data = { 153 .name = "s25fl001", 154 .parts = db1200_spiflash_parts, 155 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts), 156 .type = "m25p10", 157 }; 158 159 static struct spi_board_info db1200_spi_devs[] __initdata = { 160 { 161 /* TI TMP121AIDBVR temp sensor */ 162 .modalias = "tmp121", 163 .max_speed_hz = 2000000, 164 .bus_num = 0, 165 .chip_select = 0, 166 .mode = 0, 167 }, 168 { 169 /* Spansion S25FL001D0FMA SPI flash */ 170 .modalias = "m25p80", 171 .max_speed_hz = 50000000, 172 .bus_num = 0, 173 .chip_select = 1, 174 .mode = 0, 175 .platform_data = &db1200_spiflash_data, 176 }, 177 }; 178 179 static struct i2c_board_info db1200_i2c_devs[] __initdata = { 180 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */ 181 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 182 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */ 183 }; 184 185 /**********************************************************************/ 186 187 static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, 188 unsigned int ctrl) 189 { 190 struct nand_chip *this = mtd->priv; 191 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; 192 193 ioaddr &= 0xffffff00; 194 195 if (ctrl & NAND_CLE) { 196 ioaddr += MEM_STNAND_CMD; 197 } else if (ctrl & NAND_ALE) { 198 ioaddr += MEM_STNAND_ADDR; 199 } else { 200 /* assume we want to r/w real data by default */ 201 ioaddr += MEM_STNAND_DATA; 202 } 203 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; 204 if (cmd != NAND_CMD_NONE) { 205 __raw_writeb(cmd, this->IO_ADDR_W); 206 wmb(); 207 } 208 } 209 210 static int au1200_nand_device_ready(struct mtd_info *mtd) 211 { 212 return __raw_readl((void __iomem *)MEM_STSTAT) & 1; 213 } 214 215 static const char *db1200_part_probes[] = { "cmdlinepart", NULL }; 216 217 static struct mtd_partition db1200_nand_parts[] = { 218 { 219 .name = "NAND FS 0", 220 .offset = 0, 221 .size = 8 * 1024 * 1024, 222 }, 223 { 224 .name = "NAND FS 1", 225 .offset = MTDPART_OFS_APPEND, 226 .size = MTDPART_SIZ_FULL 227 }, 228 }; 229 230 struct platform_nand_data db1200_nand_platdata = { 231 .chip = { 232 .nr_chips = 1, 233 .chip_offset = 0, 234 .nr_partitions = ARRAY_SIZE(db1200_nand_parts), 235 .partitions = db1200_nand_parts, 236 .chip_delay = 20, 237 .part_probe_types = db1200_part_probes, 238 }, 239 .ctrl = { 240 .dev_ready = au1200_nand_device_ready, 241 .cmd_ctrl = au1200_nand_cmd_ctrl, 242 }, 243 }; 244 245 static struct resource db1200_nand_res[] = { 246 [0] = { 247 .start = DB1200_NAND_PHYS_ADDR, 248 .end = DB1200_NAND_PHYS_ADDR + 0xff, 249 .flags = IORESOURCE_MEM, 250 }, 251 }; 252 253 static struct platform_device db1200_nand_dev = { 254 .name = "gen_nand", 255 .num_resources = ARRAY_SIZE(db1200_nand_res), 256 .resource = db1200_nand_res, 257 .id = -1, 258 .dev = { 259 .platform_data = &db1200_nand_platdata, 260 } 261 }; 262 263 /**********************************************************************/ 264 265 static struct smc91x_platdata db1200_eth_data = { 266 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, 267 .leda = RPC_LED_100_10, 268 .ledb = RPC_LED_TX_RX, 269 }; 270 271 static struct resource db1200_eth_res[] = { 272 [0] = { 273 .start = DB1200_ETH_PHYS_ADDR, 274 .end = DB1200_ETH_PHYS_ADDR + 0xf, 275 .flags = IORESOURCE_MEM, 276 }, 277 [1] = { 278 .start = DB1200_ETH_INT, 279 .end = DB1200_ETH_INT, 280 .flags = IORESOURCE_IRQ, 281 }, 282 }; 283 284 static struct platform_device db1200_eth_dev = { 285 .dev = { 286 .platform_data = &db1200_eth_data, 287 }, 288 .name = "smc91x", 289 .id = -1, 290 .num_resources = ARRAY_SIZE(db1200_eth_res), 291 .resource = db1200_eth_res, 292 }; 293 294 /**********************************************************************/ 295 296 static struct resource db1200_ide_res[] = { 297 [0] = { 298 .start = DB1200_IDE_PHYS_ADDR, 299 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, 300 .flags = IORESOURCE_MEM, 301 }, 302 [1] = { 303 .start = DB1200_IDE_INT, 304 .end = DB1200_IDE_INT, 305 .flags = IORESOURCE_IRQ, 306 }, 307 [2] = { 308 .start = AU1200_DSCR_CMD0_DMA_REQ1, 309 .end = AU1200_DSCR_CMD0_DMA_REQ1, 310 .flags = IORESOURCE_DMA, 311 }, 312 }; 313 314 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32); 315 316 static struct platform_device db1200_ide_dev = { 317 .name = "au1200-ide", 318 .id = 0, 319 .dev = { 320 .dma_mask = &au1200_ide_dmamask, 321 .coherent_dma_mask = DMA_BIT_MASK(32), 322 }, 323 .num_resources = ARRAY_SIZE(db1200_ide_res), 324 .resource = db1200_ide_res, 325 }; 326 327 /**********************************************************************/ 328 329 /* SD carddetects: they're supposed to be edge-triggered, but ack 330 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one 331 * is disabled and its counterpart enabled. The 500ms timeout is 332 * because the carddetect isn't debounced in hardware. 333 */ 334 static irqreturn_t db1200_mmc_cd(int irq, void *ptr) 335 { 336 void(*mmc_cd)(struct mmc_host *, unsigned long); 337 338 if (irq == DB1200_SD0_INSERT_INT) { 339 disable_irq_nosync(DB1200_SD0_INSERT_INT); 340 enable_irq(DB1200_SD0_EJECT_INT); 341 } else { 342 disable_irq_nosync(DB1200_SD0_EJECT_INT); 343 enable_irq(DB1200_SD0_INSERT_INT); 344 } 345 346 /* link against CONFIG_MMC=m */ 347 mmc_cd = symbol_get(mmc_detect_change); 348 if (mmc_cd) { 349 mmc_cd(ptr, msecs_to_jiffies(500)); 350 symbol_put(mmc_detect_change); 351 } 352 353 return IRQ_HANDLED; 354 } 355 356 static int db1200_mmc_cd_setup(void *mmc_host, int en) 357 { 358 int ret; 359 360 if (en) { 361 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, 362 0, "sd_insert", mmc_host); 363 if (ret) 364 goto out; 365 366 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, 367 0, "sd_eject", mmc_host); 368 if (ret) { 369 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 370 goto out; 371 } 372 373 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) 374 enable_irq(DB1200_SD0_EJECT_INT); 375 else 376 enable_irq(DB1200_SD0_INSERT_INT); 377 378 } else { 379 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 380 free_irq(DB1200_SD0_EJECT_INT, mmc_host); 381 } 382 ret = 0; 383 out: 384 return ret; 385 } 386 387 static void db1200_mmc_set_power(void *mmc_host, int state) 388 { 389 if (state) { 390 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); 391 msleep(400); /* stabilization time */ 392 } else 393 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); 394 } 395 396 static int db1200_mmc_card_readonly(void *mmc_host) 397 { 398 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; 399 } 400 401 static int db1200_mmc_card_inserted(void *mmc_host) 402 { 403 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; 404 } 405 406 static void db1200_mmcled_set(struct led_classdev *led, 407 enum led_brightness brightness) 408 { 409 if (brightness != LED_OFF) 410 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 411 else 412 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 413 } 414 415 static struct led_classdev db1200_mmc_led = { 416 .brightness_set = db1200_mmcled_set, 417 }; 418 419 /* -- */ 420 421 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) 422 { 423 void(*mmc_cd)(struct mmc_host *, unsigned long); 424 425 if (irq == PB1200_SD1_INSERT_INT) { 426 disable_irq_nosync(PB1200_SD1_INSERT_INT); 427 enable_irq(PB1200_SD1_EJECT_INT); 428 } else { 429 disable_irq_nosync(PB1200_SD1_EJECT_INT); 430 enable_irq(PB1200_SD1_INSERT_INT); 431 } 432 433 /* link against CONFIG_MMC=m */ 434 mmc_cd = symbol_get(mmc_detect_change); 435 if (mmc_cd) { 436 mmc_cd(ptr, msecs_to_jiffies(500)); 437 symbol_put(mmc_detect_change); 438 } 439 440 return IRQ_HANDLED; 441 } 442 443 static int pb1200_mmc1_cd_setup(void *mmc_host, int en) 444 { 445 int ret; 446 447 if (en) { 448 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0, 449 "sd1_insert", mmc_host); 450 if (ret) 451 goto out; 452 453 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0, 454 "sd1_eject", mmc_host); 455 if (ret) { 456 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 457 goto out; 458 } 459 460 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) 461 enable_irq(PB1200_SD1_EJECT_INT); 462 else 463 enable_irq(PB1200_SD1_INSERT_INT); 464 465 } else { 466 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 467 free_irq(PB1200_SD1_EJECT_INT, mmc_host); 468 } 469 ret = 0; 470 out: 471 return ret; 472 } 473 474 static void pb1200_mmc1led_set(struct led_classdev *led, 475 enum led_brightness brightness) 476 { 477 if (brightness != LED_OFF) 478 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 479 else 480 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 481 } 482 483 static struct led_classdev pb1200_mmc1_led = { 484 .brightness_set = pb1200_mmc1led_set, 485 }; 486 487 static void pb1200_mmc1_set_power(void *mmc_host, int state) 488 { 489 if (state) { 490 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); 491 msleep(400); /* stabilization time */ 492 } else 493 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); 494 } 495 496 static int pb1200_mmc1_card_readonly(void *mmc_host) 497 { 498 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; 499 } 500 501 static int pb1200_mmc1_card_inserted(void *mmc_host) 502 { 503 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 504 } 505 506 507 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = { 508 [0] = { 509 .cd_setup = db1200_mmc_cd_setup, 510 .set_power = db1200_mmc_set_power, 511 .card_inserted = db1200_mmc_card_inserted, 512 .card_readonly = db1200_mmc_card_readonly, 513 .led = &db1200_mmc_led, 514 }, 515 [1] = { 516 .cd_setup = pb1200_mmc1_cd_setup, 517 .set_power = pb1200_mmc1_set_power, 518 .card_inserted = pb1200_mmc1_card_inserted, 519 .card_readonly = pb1200_mmc1_card_readonly, 520 .led = &pb1200_mmc1_led, 521 }, 522 }; 523 524 static struct resource au1200_mmc0_resources[] = { 525 [0] = { 526 .start = AU1100_SD0_PHYS_ADDR, 527 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 528 .flags = IORESOURCE_MEM, 529 }, 530 [1] = { 531 .start = AU1200_SD_INT, 532 .end = AU1200_SD_INT, 533 .flags = IORESOURCE_IRQ, 534 }, 535 [2] = { 536 .start = AU1200_DSCR_CMD0_SDMS_TX0, 537 .end = AU1200_DSCR_CMD0_SDMS_TX0, 538 .flags = IORESOURCE_DMA, 539 }, 540 [3] = { 541 .start = AU1200_DSCR_CMD0_SDMS_RX0, 542 .end = AU1200_DSCR_CMD0_SDMS_RX0, 543 .flags = IORESOURCE_DMA, 544 } 545 }; 546 547 static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 548 549 static struct platform_device db1200_mmc0_dev = { 550 .name = "au1xxx-mmc", 551 .id = 0, 552 .dev = { 553 .dma_mask = &au1xxx_mmc_dmamask, 554 .coherent_dma_mask = DMA_BIT_MASK(32), 555 .platform_data = &db1200_mmc_platdata[0], 556 }, 557 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 558 .resource = au1200_mmc0_resources, 559 }; 560 561 static struct resource au1200_mmc1_res[] = { 562 [0] = { 563 .start = AU1100_SD1_PHYS_ADDR, 564 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 565 .flags = IORESOURCE_MEM, 566 }, 567 [1] = { 568 .start = AU1200_SD_INT, 569 .end = AU1200_SD_INT, 570 .flags = IORESOURCE_IRQ, 571 }, 572 [2] = { 573 .start = AU1200_DSCR_CMD0_SDMS_TX1, 574 .end = AU1200_DSCR_CMD0_SDMS_TX1, 575 .flags = IORESOURCE_DMA, 576 }, 577 [3] = { 578 .start = AU1200_DSCR_CMD0_SDMS_RX1, 579 .end = AU1200_DSCR_CMD0_SDMS_RX1, 580 .flags = IORESOURCE_DMA, 581 } 582 }; 583 584 static struct platform_device pb1200_mmc1_dev = { 585 .name = "au1xxx-mmc", 586 .id = 1, 587 .dev = { 588 .dma_mask = &au1xxx_mmc_dmamask, 589 .coherent_dma_mask = DMA_BIT_MASK(32), 590 .platform_data = &db1200_mmc_platdata[1], 591 }, 592 .num_resources = ARRAY_SIZE(au1200_mmc1_res), 593 .resource = au1200_mmc1_res, 594 }; 595 596 /**********************************************************************/ 597 598 static int db1200fb_panel_index(void) 599 { 600 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; 601 } 602 603 static int db1200fb_panel_init(void) 604 { 605 /* Apply power */ 606 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 607 BCSR_BOARD_LCDBL); 608 return 0; 609 } 610 611 static int db1200fb_panel_shutdown(void) 612 { 613 /* Remove power */ 614 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 615 BCSR_BOARD_LCDBL, 0); 616 return 0; 617 } 618 619 static struct au1200fb_platdata db1200fb_pd = { 620 .panel_index = db1200fb_panel_index, 621 .panel_init = db1200fb_panel_init, 622 .panel_shutdown = db1200fb_panel_shutdown, 623 }; 624 625 static struct resource au1200_lcd_res[] = { 626 [0] = { 627 .start = AU1200_LCD_PHYS_ADDR, 628 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 629 .flags = IORESOURCE_MEM, 630 }, 631 [1] = { 632 .start = AU1200_LCD_INT, 633 .end = AU1200_LCD_INT, 634 .flags = IORESOURCE_IRQ, 635 } 636 }; 637 638 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); 639 640 static struct platform_device au1200_lcd_dev = { 641 .name = "au1200-lcd", 642 .id = 0, 643 .dev = { 644 .dma_mask = &au1200_lcd_dmamask, 645 .coherent_dma_mask = DMA_BIT_MASK(32), 646 .platform_data = &db1200fb_pd, 647 }, 648 .num_resources = ARRAY_SIZE(au1200_lcd_res), 649 .resource = au1200_lcd_res, 650 }; 651 652 /**********************************************************************/ 653 654 static struct resource au1200_psc0_res[] = { 655 [0] = { 656 .start = AU1550_PSC0_PHYS_ADDR, 657 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 658 .flags = IORESOURCE_MEM, 659 }, 660 [1] = { 661 .start = AU1200_PSC0_INT, 662 .end = AU1200_PSC0_INT, 663 .flags = IORESOURCE_IRQ, 664 }, 665 [2] = { 666 .start = AU1200_DSCR_CMD0_PSC0_TX, 667 .end = AU1200_DSCR_CMD0_PSC0_TX, 668 .flags = IORESOURCE_DMA, 669 }, 670 [3] = { 671 .start = AU1200_DSCR_CMD0_PSC0_RX, 672 .end = AU1200_DSCR_CMD0_PSC0_RX, 673 .flags = IORESOURCE_DMA, 674 }, 675 }; 676 677 static struct platform_device db1200_i2c_dev = { 678 .name = "au1xpsc_smbus", 679 .id = 0, /* bus number */ 680 .num_resources = ARRAY_SIZE(au1200_psc0_res), 681 .resource = au1200_psc0_res, 682 }; 683 684 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 685 { 686 if (cs) 687 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL); 688 else 689 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0); 690 } 691 692 static struct au1550_spi_info db1200_spi_platdata = { 693 .mainclk_hz = 50000000, /* PSC0 clock */ 694 .num_chipselect = 2, 695 .activate_cs = db1200_spi_cs_en, 696 }; 697 698 static u64 spi_dmamask = DMA_BIT_MASK(32); 699 700 static struct platform_device db1200_spi_dev = { 701 .dev = { 702 .dma_mask = &spi_dmamask, 703 .coherent_dma_mask = DMA_BIT_MASK(32), 704 .platform_data = &db1200_spi_platdata, 705 }, 706 .name = "au1550-spi", 707 .id = 0, /* bus number */ 708 .num_resources = ARRAY_SIZE(au1200_psc0_res), 709 .resource = au1200_psc0_res, 710 }; 711 712 static struct resource au1200_psc1_res[] = { 713 [0] = { 714 .start = AU1550_PSC1_PHYS_ADDR, 715 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 716 .flags = IORESOURCE_MEM, 717 }, 718 [1] = { 719 .start = AU1200_PSC1_INT, 720 .end = AU1200_PSC1_INT, 721 .flags = IORESOURCE_IRQ, 722 }, 723 [2] = { 724 .start = AU1200_DSCR_CMD0_PSC1_TX, 725 .end = AU1200_DSCR_CMD0_PSC1_TX, 726 .flags = IORESOURCE_DMA, 727 }, 728 [3] = { 729 .start = AU1200_DSCR_CMD0_PSC1_RX, 730 .end = AU1200_DSCR_CMD0_PSC1_RX, 731 .flags = IORESOURCE_DMA, 732 }, 733 }; 734 735 /* AC97 or I2S device */ 736 static struct platform_device db1200_audio_dev = { 737 /* name assigned later based on switch setting */ 738 .id = 1, /* PSC ID */ 739 .num_resources = ARRAY_SIZE(au1200_psc1_res), 740 .resource = au1200_psc1_res, 741 }; 742 743 /* DB1200 ASoC card device */ 744 static struct platform_device db1200_sound_dev = { 745 /* name assigned later based on switch setting */ 746 .id = 1, /* PSC ID */ 747 }; 748 749 static struct platform_device db1200_stac_dev = { 750 .name = "ac97-codec", 751 .id = 1, /* on PSC1 */ 752 }; 753 754 static struct platform_device db1200_audiodma_dev = { 755 .name = "au1xpsc-pcm", 756 .id = 1, /* PSC ID */ 757 }; 758 759 static struct platform_device *db1200_devs[] __initdata = { 760 NULL, /* PSC0, selected by S6.8 */ 761 &db1200_ide_dev, 762 &db1200_mmc0_dev, 763 &au1200_lcd_dev, 764 &db1200_eth_dev, 765 &db1200_nand_dev, 766 &db1200_audiodma_dev, 767 &db1200_audio_dev, 768 &db1200_stac_dev, 769 &db1200_sound_dev, 770 }; 771 772 static struct platform_device *pb1200_devs[] __initdata = { 773 &pb1200_mmc1_dev, 774 }; 775 776 /* Some peripheral base addresses differ on the PB1200 */ 777 static int __init pb1200_res_fixup(void) 778 { 779 /* CPLD Revs earlier than 4 cause problems */ 780 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { 781 printk(KERN_ERR "WARNING!!!\n"); 782 printk(KERN_ERR "WARNING!!!\n"); 783 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n"); 784 printk(KERN_ERR "the board updated to latest revisions.\n"); 785 printk(KERN_ERR "This software will not work reliably\n"); 786 printk(KERN_ERR "on anything older than CPLD rev 4.!\n"); 787 printk(KERN_ERR "WARNING!!!\n"); 788 printk(KERN_ERR "WARNING!!!\n"); 789 return 1; 790 } 791 792 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; 793 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; 794 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; 795 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; 796 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; 797 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; 798 return 0; 799 } 800 801 static int __init db1200_dev_init(void) 802 { 803 unsigned long pfc; 804 unsigned short sw; 805 int swapped, bid; 806 807 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 808 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 809 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 810 if (pb1200_res_fixup()) 811 return -ENODEV; 812 } 813 814 /* GPIO7 is low-level triggered CPLD cascade */ 815 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); 816 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 817 818 /* insert/eject pairs: one of both is always screaming. To avoid 819 * issues they must not be automatically enabled when initially 820 * requested. 821 */ 822 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); 823 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); 824 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); 825 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); 826 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); 827 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); 828 829 i2c_register_board_info(0, db1200_i2c_devs, 830 ARRAY_SIZE(db1200_i2c_devs)); 831 spi_register_board_info(db1200_spi_devs, 832 ARRAY_SIZE(db1200_i2c_devs)); 833 834 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 835 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 836 * or S12 on the PB1200. 837 */ 838 839 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 840 * this pin is claimed by PSC0 (unused though, but pinmux doesn't 841 * allow to free it without crippling the SPI interface). 842 * As a result, in SPI mode, OTG simply won't work (PSC0 uses 843 * it as an input pin which is pulled high on the boards). 844 */ 845 pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A; 846 847 /* switch off OTG VBUS supply */ 848 gpio_request(215, "otg-vbus"); 849 gpio_direction_output(215, 1); 850 851 printk(KERN_INFO "%s device configuration:\n", board_type_str()); 852 853 sw = bcsr_read(BCSR_SWITCHES); 854 if (sw & BCSR_SWITCHES_DIP_8) { 855 db1200_devs[0] = &db1200_i2c_dev; 856 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); 857 858 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ 859 860 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); 861 printk(KERN_INFO " OTG port VBUS supply available!\n"); 862 } else { 863 db1200_devs[0] = &db1200_spi_dev; 864 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); 865 866 pfc |= (1 << 17); /* PSC0 owns GPIO215 */ 867 868 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); 869 printk(KERN_INFO " OTG port VBUS supply disabled\n"); 870 } 871 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); 872 wmb(); 873 874 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! 875 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S 876 */ 877 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; 878 if (sw == BCSR_SWITCHES_DIP_8) { 879 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); 880 db1200_audio_dev.name = "au1xpsc_i2s"; 881 db1200_sound_dev.name = "db1200-i2s"; 882 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); 883 } else { 884 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); 885 db1200_audio_dev.name = "au1xpsc_ac97"; 886 db1200_sound_dev.name = "db1200-ac97"; 887 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); 888 } 889 890 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 891 __raw_writel(PSC_SEL_CLK_SERCLK, 892 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 893 wmb(); 894 895 db1x_register_pcmcia_socket( 896 AU1000_PCMCIA_ATTR_PHYS_ADDR, 897 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 898 AU1000_PCMCIA_MEM_PHYS_ADDR, 899 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 900 AU1000_PCMCIA_IO_PHYS_ADDR, 901 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 902 DB1200_PC0_INT, DB1200_PC0_INSERT_INT, 903 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); 904 905 db1x_register_pcmcia_socket( 906 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 907 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 908 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 909 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 910 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 911 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 912 DB1200_PC1_INT, DB1200_PC1_INSERT_INT, 913 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); 914 915 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 916 db1x_register_norflash(64 << 20, 2, swapped); 917 918 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 919 920 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ 921 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 922 (bid == BCSR_WHOAMI_PB1200_DDR2)) 923 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); 924 925 return 0; 926 } 927 device_initcall(db1200_dev_init); 928