1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DBAu1200/PBAu1200 board platform device registration 4 * 5 * Copyright (C) 2008-2011 Manuel Lauss 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/gpio.h> 11 #include <linux/i2c.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/leds.h> 16 #include <linux/mmc/host.h> 17 #include <linux/mtd/mtd.h> 18 #include <linux/mtd/platnand.h> 19 #include <linux/platform_device.h> 20 #include <linux/serial_8250.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/flash.h> 23 #include <linux/smc91x.h> 24 #include <linux/ata_platform.h> 25 #include <asm/mach-au1x00/au1000.h> 26 #include <asm/mach-au1x00/au1100_mmc.h> 27 #include <asm/mach-au1x00/au1xxx_dbdma.h> 28 #include <asm/mach-au1x00/au1xxx_psc.h> 29 #include <asm/mach-au1x00/au1200fb.h> 30 #include <asm/mach-au1x00/au1550_spi.h> 31 #include <asm/mach-db1x00/bcsr.h> 32 33 #include "platform.h" 34 35 #define BCSR_INT_IDE 0x0001 36 #define BCSR_INT_ETH 0x0002 37 #define BCSR_INT_PC0 0x0004 38 #define BCSR_INT_PC0STSCHG 0x0008 39 #define BCSR_INT_PC1 0x0010 40 #define BCSR_INT_PC1STSCHG 0x0020 41 #define BCSR_INT_DC 0x0040 42 #define BCSR_INT_FLASHBUSY 0x0080 43 #define BCSR_INT_PC0INSERT 0x0100 44 #define BCSR_INT_PC0EJECT 0x0200 45 #define BCSR_INT_PC1INSERT 0x0400 46 #define BCSR_INT_PC1EJECT 0x0800 47 #define BCSR_INT_SD0INSERT 0x1000 48 #define BCSR_INT_SD0EJECT 0x2000 49 #define BCSR_INT_SD1INSERT 0x4000 50 #define BCSR_INT_SD1EJECT 0x8000 51 52 #define DB1200_IDE_PHYS_ADDR 0x18800000 53 #define DB1200_IDE_REG_SHIFT 5 54 #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT) 55 #define DB1200_ETH_PHYS_ADDR 0x19000300 56 #define DB1200_NAND_PHYS_ADDR 0x20000000 57 58 #define PB1200_IDE_PHYS_ADDR 0x0C800000 59 #define PB1200_ETH_PHYS_ADDR 0x0D000300 60 #define PB1200_NAND_PHYS_ADDR 0x1C000000 61 62 #define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1) 63 #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) 64 #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) 65 #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) 66 #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) 67 #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) 68 #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) 69 #define DB1200_DC_INT (DB1200_INT_BEGIN + 6) 70 #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) 71 #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) 72 #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) 73 #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) 74 #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) 75 #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) 76 #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) 77 #define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14) 78 #define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15) 79 #define DB1200_INT_END (DB1200_INT_BEGIN + 15) 80 81 const char *get_system_type(void); 82 83 static int __init db1200_detect_board(void) 84 { 85 int bid; 86 87 /* try the DB1200 first */ 88 bcsr_init(DB1200_BCSR_PHYS_ADDR, 89 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); 90 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { 91 unsigned short t = bcsr_read(BCSR_HEXLEDS); 92 bcsr_write(BCSR_HEXLEDS, ~t); 93 if (bcsr_read(BCSR_HEXLEDS) != t) { 94 bcsr_write(BCSR_HEXLEDS, t); 95 return 0; 96 } 97 } 98 99 /* okay, try the PB1200 then */ 100 bcsr_init(PB1200_BCSR_PHYS_ADDR, 101 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); 102 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 103 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 104 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 105 unsigned short t = bcsr_read(BCSR_HEXLEDS); 106 bcsr_write(BCSR_HEXLEDS, ~t); 107 if (bcsr_read(BCSR_HEXLEDS) != t) { 108 bcsr_write(BCSR_HEXLEDS, t); 109 return 0; 110 } 111 } 112 113 return 1; /* it's neither */ 114 } 115 116 int __init db1200_board_setup(void) 117 { 118 unsigned short whoami; 119 120 if (db1200_detect_board()) 121 return -ENODEV; 122 123 whoami = bcsr_read(BCSR_WHOAMI); 124 switch (BCSR_WHOAMI_BOARD(whoami)) { 125 case BCSR_WHOAMI_PB1200_DDR1: 126 case BCSR_WHOAMI_PB1200_DDR2: 127 case BCSR_WHOAMI_DB1200: 128 break; 129 default: 130 return -ENODEV; 131 } 132 133 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" 134 " Board-ID %d Daughtercard ID %d\n", get_system_type(), 135 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 136 137 return 0; 138 } 139 140 /******************************************************************************/ 141 142 static u64 au1200_all_dmamask = DMA_BIT_MASK(32); 143 144 static struct mtd_partition db1200_spiflash_parts[] = { 145 { 146 .name = "spi_flash", 147 .offset = 0, 148 .size = MTDPART_SIZ_FULL, 149 }, 150 }; 151 152 static struct flash_platform_data db1200_spiflash_data = { 153 .name = "s25fl001", 154 .parts = db1200_spiflash_parts, 155 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts), 156 .type = "m25p10", 157 }; 158 159 static struct spi_board_info db1200_spi_devs[] __initdata = { 160 { 161 /* TI TMP121AIDBVR temp sensor */ 162 .modalias = "tmp121", 163 .max_speed_hz = 2000000, 164 .bus_num = 0, 165 .chip_select = 0, 166 .mode = 0, 167 }, 168 { 169 /* Spansion S25FL001D0FMA SPI flash */ 170 .modalias = "m25p80", 171 .max_speed_hz = 50000000, 172 .bus_num = 0, 173 .chip_select = 1, 174 .mode = 0, 175 .platform_data = &db1200_spiflash_data, 176 }, 177 }; 178 179 static struct i2c_board_info db1200_i2c_devs[] __initdata = { 180 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */ 181 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 182 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */ 183 }; 184 185 /**********************************************************************/ 186 187 static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd, 188 unsigned int ctrl) 189 { 190 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W; 191 192 ioaddr &= 0xffffff00; 193 194 if (ctrl & NAND_CLE) { 195 ioaddr += MEM_STNAND_CMD; 196 } else if (ctrl & NAND_ALE) { 197 ioaddr += MEM_STNAND_ADDR; 198 } else { 199 /* assume we want to r/w real data by default */ 200 ioaddr += MEM_STNAND_DATA; 201 } 202 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr; 203 if (cmd != NAND_CMD_NONE) { 204 __raw_writeb(cmd, this->legacy.IO_ADDR_W); 205 wmb(); 206 } 207 } 208 209 static int au1200_nand_device_ready(struct nand_chip *this) 210 { 211 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 212 } 213 214 static struct mtd_partition db1200_nand_parts[] = { 215 { 216 .name = "NAND FS 0", 217 .offset = 0, 218 .size = 8 * 1024 * 1024, 219 }, 220 { 221 .name = "NAND FS 1", 222 .offset = MTDPART_OFS_APPEND, 223 .size = MTDPART_SIZ_FULL 224 }, 225 }; 226 227 struct platform_nand_data db1200_nand_platdata = { 228 .chip = { 229 .nr_chips = 1, 230 .chip_offset = 0, 231 .nr_partitions = ARRAY_SIZE(db1200_nand_parts), 232 .partitions = db1200_nand_parts, 233 .chip_delay = 20, 234 }, 235 .ctrl = { 236 .dev_ready = au1200_nand_device_ready, 237 .cmd_ctrl = au1200_nand_cmd_ctrl, 238 }, 239 }; 240 241 static struct resource db1200_nand_res[] = { 242 [0] = { 243 .start = DB1200_NAND_PHYS_ADDR, 244 .end = DB1200_NAND_PHYS_ADDR + 0xff, 245 .flags = IORESOURCE_MEM, 246 }, 247 }; 248 249 static struct platform_device db1200_nand_dev = { 250 .name = "gen_nand", 251 .num_resources = ARRAY_SIZE(db1200_nand_res), 252 .resource = db1200_nand_res, 253 .id = -1, 254 .dev = { 255 .platform_data = &db1200_nand_platdata, 256 } 257 }; 258 259 /**********************************************************************/ 260 261 static struct smc91x_platdata db1200_eth_data = { 262 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, 263 .leda = RPC_LED_100_10, 264 .ledb = RPC_LED_TX_RX, 265 }; 266 267 static struct resource db1200_eth_res[] = { 268 [0] = { 269 .start = DB1200_ETH_PHYS_ADDR, 270 .end = DB1200_ETH_PHYS_ADDR + 0xf, 271 .flags = IORESOURCE_MEM, 272 }, 273 [1] = { 274 .start = DB1200_ETH_INT, 275 .end = DB1200_ETH_INT, 276 .flags = IORESOURCE_IRQ, 277 }, 278 }; 279 280 static struct platform_device db1200_eth_dev = { 281 .dev = { 282 .platform_data = &db1200_eth_data, 283 }, 284 .name = "smc91x", 285 .id = -1, 286 .num_resources = ARRAY_SIZE(db1200_eth_res), 287 .resource = db1200_eth_res, 288 }; 289 290 /**********************************************************************/ 291 292 static struct pata_platform_info db1200_ide_info = { 293 .ioport_shift = DB1200_IDE_REG_SHIFT, 294 }; 295 296 #define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT) 297 static struct resource db1200_ide_res[] = { 298 [0] = { 299 .start = DB1200_IDE_PHYS_ADDR, 300 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1, 301 .flags = IORESOURCE_MEM, 302 }, 303 [1] = { 304 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START, 305 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, 306 .flags = IORESOURCE_MEM, 307 }, 308 [2] = { 309 .start = DB1200_IDE_INT, 310 .end = DB1200_IDE_INT, 311 .flags = IORESOURCE_IRQ, 312 }, 313 }; 314 315 static struct platform_device db1200_ide_dev = { 316 .name = "pata_platform", 317 .id = 0, 318 .dev = { 319 .dma_mask = &au1200_all_dmamask, 320 .coherent_dma_mask = DMA_BIT_MASK(32), 321 .platform_data = &db1200_ide_info, 322 }, 323 .num_resources = ARRAY_SIZE(db1200_ide_res), 324 .resource = db1200_ide_res, 325 }; 326 327 /**********************************************************************/ 328 329 /* SD carddetects: they're supposed to be edge-triggered, but ack 330 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one 331 * is disabled and its counterpart enabled. The 200ms timeout is 332 * because the carddetect usually triggers twice, after debounce. 333 */ 334 static irqreturn_t db1200_mmc_cd(int irq, void *ptr) 335 { 336 disable_irq_nosync(irq); 337 return IRQ_WAKE_THREAD; 338 } 339 340 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr) 341 { 342 mmc_detect_change(ptr, msecs_to_jiffies(200)); 343 344 msleep(100); /* debounce */ 345 if (irq == DB1200_SD0_INSERT_INT) 346 enable_irq(DB1200_SD0_EJECT_INT); 347 else 348 enable_irq(DB1200_SD0_INSERT_INT); 349 350 return IRQ_HANDLED; 351 } 352 353 static int db1200_mmc_cd_setup(void *mmc_host, int en) 354 { 355 int ret; 356 357 if (en) { 358 ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, 359 db1200_mmc_cdfn, 0, "sd_insert", mmc_host); 360 if (ret) 361 goto out; 362 363 ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, 364 db1200_mmc_cdfn, 0, "sd_eject", mmc_host); 365 if (ret) { 366 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 367 goto out; 368 } 369 370 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) 371 enable_irq(DB1200_SD0_EJECT_INT); 372 else 373 enable_irq(DB1200_SD0_INSERT_INT); 374 375 } else { 376 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 377 free_irq(DB1200_SD0_EJECT_INT, mmc_host); 378 } 379 ret = 0; 380 out: 381 return ret; 382 } 383 384 static void db1200_mmc_set_power(void *mmc_host, int state) 385 { 386 if (state) { 387 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); 388 msleep(400); /* stabilization time */ 389 } else 390 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); 391 } 392 393 static int db1200_mmc_card_readonly(void *mmc_host) 394 { 395 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; 396 } 397 398 static int db1200_mmc_card_inserted(void *mmc_host) 399 { 400 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; 401 } 402 403 static void db1200_mmcled_set(struct led_classdev *led, 404 enum led_brightness brightness) 405 { 406 if (brightness != LED_OFF) 407 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 408 else 409 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 410 } 411 412 static struct led_classdev db1200_mmc_led = { 413 .brightness_set = db1200_mmcled_set, 414 }; 415 416 /* -- */ 417 418 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) 419 { 420 disable_irq_nosync(irq); 421 return IRQ_WAKE_THREAD; 422 } 423 424 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr) 425 { 426 mmc_detect_change(ptr, msecs_to_jiffies(200)); 427 428 msleep(100); /* debounce */ 429 if (irq == PB1200_SD1_INSERT_INT) 430 enable_irq(PB1200_SD1_EJECT_INT); 431 else 432 enable_irq(PB1200_SD1_INSERT_INT); 433 434 return IRQ_HANDLED; 435 } 436 437 static int pb1200_mmc1_cd_setup(void *mmc_host, int en) 438 { 439 int ret; 440 441 if (en) { 442 ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 443 pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host); 444 if (ret) 445 goto out; 446 447 ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 448 pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host); 449 if (ret) { 450 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 451 goto out; 452 } 453 454 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) 455 enable_irq(PB1200_SD1_EJECT_INT); 456 else 457 enable_irq(PB1200_SD1_INSERT_INT); 458 459 } else { 460 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 461 free_irq(PB1200_SD1_EJECT_INT, mmc_host); 462 } 463 ret = 0; 464 out: 465 return ret; 466 } 467 468 static void pb1200_mmc1led_set(struct led_classdev *led, 469 enum led_brightness brightness) 470 { 471 if (brightness != LED_OFF) 472 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 473 else 474 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 475 } 476 477 static struct led_classdev pb1200_mmc1_led = { 478 .brightness_set = pb1200_mmc1led_set, 479 }; 480 481 static void pb1200_mmc1_set_power(void *mmc_host, int state) 482 { 483 if (state) { 484 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); 485 msleep(400); /* stabilization time */ 486 } else 487 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); 488 } 489 490 static int pb1200_mmc1_card_readonly(void *mmc_host) 491 { 492 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; 493 } 494 495 static int pb1200_mmc1_card_inserted(void *mmc_host) 496 { 497 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 498 } 499 500 501 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = { 502 [0] = { 503 .cd_setup = db1200_mmc_cd_setup, 504 .set_power = db1200_mmc_set_power, 505 .card_inserted = db1200_mmc_card_inserted, 506 .card_readonly = db1200_mmc_card_readonly, 507 .led = &db1200_mmc_led, 508 }, 509 [1] = { 510 .cd_setup = pb1200_mmc1_cd_setup, 511 .set_power = pb1200_mmc1_set_power, 512 .card_inserted = pb1200_mmc1_card_inserted, 513 .card_readonly = pb1200_mmc1_card_readonly, 514 .led = &pb1200_mmc1_led, 515 }, 516 }; 517 518 static struct resource au1200_mmc0_resources[] = { 519 [0] = { 520 .start = AU1100_SD0_PHYS_ADDR, 521 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 522 .flags = IORESOURCE_MEM, 523 }, 524 [1] = { 525 .start = AU1200_SD_INT, 526 .end = AU1200_SD_INT, 527 .flags = IORESOURCE_IRQ, 528 }, 529 [2] = { 530 .start = AU1200_DSCR_CMD0_SDMS_TX0, 531 .end = AU1200_DSCR_CMD0_SDMS_TX0, 532 .flags = IORESOURCE_DMA, 533 }, 534 [3] = { 535 .start = AU1200_DSCR_CMD0_SDMS_RX0, 536 .end = AU1200_DSCR_CMD0_SDMS_RX0, 537 .flags = IORESOURCE_DMA, 538 } 539 }; 540 541 static struct platform_device db1200_mmc0_dev = { 542 .name = "au1xxx-mmc", 543 .id = 0, 544 .dev = { 545 .dma_mask = &au1200_all_dmamask, 546 .coherent_dma_mask = DMA_BIT_MASK(32), 547 .platform_data = &db1200_mmc_platdata[0], 548 }, 549 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 550 .resource = au1200_mmc0_resources, 551 }; 552 553 static struct resource au1200_mmc1_res[] = { 554 [0] = { 555 .start = AU1100_SD1_PHYS_ADDR, 556 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 557 .flags = IORESOURCE_MEM, 558 }, 559 [1] = { 560 .start = AU1200_SD_INT, 561 .end = AU1200_SD_INT, 562 .flags = IORESOURCE_IRQ, 563 }, 564 [2] = { 565 .start = AU1200_DSCR_CMD0_SDMS_TX1, 566 .end = AU1200_DSCR_CMD0_SDMS_TX1, 567 .flags = IORESOURCE_DMA, 568 }, 569 [3] = { 570 .start = AU1200_DSCR_CMD0_SDMS_RX1, 571 .end = AU1200_DSCR_CMD0_SDMS_RX1, 572 .flags = IORESOURCE_DMA, 573 } 574 }; 575 576 static struct platform_device pb1200_mmc1_dev = { 577 .name = "au1xxx-mmc", 578 .id = 1, 579 .dev = { 580 .dma_mask = &au1200_all_dmamask, 581 .coherent_dma_mask = DMA_BIT_MASK(32), 582 .platform_data = &db1200_mmc_platdata[1], 583 }, 584 .num_resources = ARRAY_SIZE(au1200_mmc1_res), 585 .resource = au1200_mmc1_res, 586 }; 587 588 /**********************************************************************/ 589 590 static int db1200fb_panel_index(void) 591 { 592 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; 593 } 594 595 static int db1200fb_panel_init(void) 596 { 597 /* Apply power */ 598 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 599 BCSR_BOARD_LCDBL); 600 return 0; 601 } 602 603 static int db1200fb_panel_shutdown(void) 604 { 605 /* Remove power */ 606 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 607 BCSR_BOARD_LCDBL, 0); 608 return 0; 609 } 610 611 static struct au1200fb_platdata db1200fb_pd = { 612 .panel_index = db1200fb_panel_index, 613 .panel_init = db1200fb_panel_init, 614 .panel_shutdown = db1200fb_panel_shutdown, 615 }; 616 617 static struct resource au1200_lcd_res[] = { 618 [0] = { 619 .start = AU1200_LCD_PHYS_ADDR, 620 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 621 .flags = IORESOURCE_MEM, 622 }, 623 [1] = { 624 .start = AU1200_LCD_INT, 625 .end = AU1200_LCD_INT, 626 .flags = IORESOURCE_IRQ, 627 } 628 }; 629 630 static struct platform_device au1200_lcd_dev = { 631 .name = "au1200-lcd", 632 .id = 0, 633 .dev = { 634 .dma_mask = &au1200_all_dmamask, 635 .coherent_dma_mask = DMA_BIT_MASK(32), 636 .platform_data = &db1200fb_pd, 637 }, 638 .num_resources = ARRAY_SIZE(au1200_lcd_res), 639 .resource = au1200_lcd_res, 640 }; 641 642 /**********************************************************************/ 643 644 static struct resource au1200_psc0_res[] = { 645 [0] = { 646 .start = AU1550_PSC0_PHYS_ADDR, 647 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 648 .flags = IORESOURCE_MEM, 649 }, 650 [1] = { 651 .start = AU1200_PSC0_INT, 652 .end = AU1200_PSC0_INT, 653 .flags = IORESOURCE_IRQ, 654 }, 655 [2] = { 656 .start = AU1200_DSCR_CMD0_PSC0_TX, 657 .end = AU1200_DSCR_CMD0_PSC0_TX, 658 .flags = IORESOURCE_DMA, 659 }, 660 [3] = { 661 .start = AU1200_DSCR_CMD0_PSC0_RX, 662 .end = AU1200_DSCR_CMD0_PSC0_RX, 663 .flags = IORESOURCE_DMA, 664 }, 665 }; 666 667 static struct platform_device db1200_i2c_dev = { 668 .name = "au1xpsc_smbus", 669 .id = 0, /* bus number */ 670 .num_resources = ARRAY_SIZE(au1200_psc0_res), 671 .resource = au1200_psc0_res, 672 }; 673 674 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 675 { 676 if (cs) 677 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL); 678 else 679 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0); 680 } 681 682 static struct au1550_spi_info db1200_spi_platdata = { 683 .mainclk_hz = 50000000, /* PSC0 clock */ 684 .num_chipselect = 2, 685 .activate_cs = db1200_spi_cs_en, 686 }; 687 688 static struct platform_device db1200_spi_dev = { 689 .dev = { 690 .dma_mask = &au1200_all_dmamask, 691 .coherent_dma_mask = DMA_BIT_MASK(32), 692 .platform_data = &db1200_spi_platdata, 693 }, 694 .name = "au1550-spi", 695 .id = 0, /* bus number */ 696 .num_resources = ARRAY_SIZE(au1200_psc0_res), 697 .resource = au1200_psc0_res, 698 }; 699 700 static struct resource au1200_psc1_res[] = { 701 [0] = { 702 .start = AU1550_PSC1_PHYS_ADDR, 703 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 704 .flags = IORESOURCE_MEM, 705 }, 706 [1] = { 707 .start = AU1200_PSC1_INT, 708 .end = AU1200_PSC1_INT, 709 .flags = IORESOURCE_IRQ, 710 }, 711 [2] = { 712 .start = AU1200_DSCR_CMD0_PSC1_TX, 713 .end = AU1200_DSCR_CMD0_PSC1_TX, 714 .flags = IORESOURCE_DMA, 715 }, 716 [3] = { 717 .start = AU1200_DSCR_CMD0_PSC1_RX, 718 .end = AU1200_DSCR_CMD0_PSC1_RX, 719 .flags = IORESOURCE_DMA, 720 }, 721 }; 722 723 /* AC97 or I2S device */ 724 static struct platform_device db1200_audio_dev = { 725 /* name assigned later based on switch setting */ 726 .id = 1, /* PSC ID */ 727 .num_resources = ARRAY_SIZE(au1200_psc1_res), 728 .resource = au1200_psc1_res, 729 }; 730 731 /* DB1200 ASoC card device */ 732 static struct platform_device db1200_sound_dev = { 733 /* name assigned later based on switch setting */ 734 .id = 1, /* PSC ID */ 735 .dev = { 736 .dma_mask = &au1200_all_dmamask, 737 .coherent_dma_mask = DMA_BIT_MASK(32), 738 }, 739 }; 740 741 static struct platform_device db1200_stac_dev = { 742 .name = "ac97-codec", 743 .id = 1, /* on PSC1 */ 744 }; 745 746 static struct platform_device db1200_audiodma_dev = { 747 .name = "au1xpsc-pcm", 748 .id = 1, /* PSC ID */ 749 }; 750 751 static struct platform_device *db1200_devs[] __initdata = { 752 NULL, /* PSC0, selected by S6.8 */ 753 &db1200_ide_dev, 754 &db1200_mmc0_dev, 755 &au1200_lcd_dev, 756 &db1200_eth_dev, 757 &db1200_nand_dev, 758 &db1200_audiodma_dev, 759 &db1200_audio_dev, 760 &db1200_stac_dev, 761 &db1200_sound_dev, 762 }; 763 764 static struct platform_device *pb1200_devs[] __initdata = { 765 &pb1200_mmc1_dev, 766 }; 767 768 /* Some peripheral base addresses differ on the PB1200 */ 769 static int __init pb1200_res_fixup(void) 770 { 771 /* CPLD Revs earlier than 4 cause problems */ 772 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { 773 printk(KERN_ERR "WARNING!!!\n"); 774 printk(KERN_ERR "WARNING!!!\n"); 775 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n"); 776 printk(KERN_ERR "the board updated to latest revisions.\n"); 777 printk(KERN_ERR "This software will not work reliably\n"); 778 printk(KERN_ERR "on anything older than CPLD rev 4.!\n"); 779 printk(KERN_ERR "WARNING!!!\n"); 780 printk(KERN_ERR "WARNING!!!\n"); 781 return 1; 782 } 783 784 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; 785 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; 786 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; 787 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; 788 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; 789 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; 790 return 0; 791 } 792 793 int __init db1200_dev_setup(void) 794 { 795 unsigned long pfc; 796 unsigned short sw; 797 int swapped, bid; 798 struct clk *c; 799 800 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 801 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 802 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 803 if (pb1200_res_fixup()) 804 return -ENODEV; 805 } 806 807 /* GPIO7 is low-level triggered CPLD cascade */ 808 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); 809 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 810 811 /* SMBus/SPI on PSC0, Audio on PSC1 */ 812 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC); 813 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); 814 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); 815 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ 816 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 817 818 /* get 50MHz for I2C driver on PSC0 */ 819 c = clk_get(NULL, "psc0_intclk"); 820 if (!IS_ERR(c)) { 821 pfc = clk_round_rate(c, 50000000); 822 if ((pfc < 1) || (abs(50000000 - pfc) > 2500000)) 823 pr_warn("DB1200: can't get I2C close to 50MHz\n"); 824 else 825 clk_set_rate(c, pfc); 826 clk_prepare_enable(c); 827 clk_put(c); 828 } 829 830 /* insert/eject pairs: one of both is always screaming. To avoid 831 * issues they must not be automatically enabled when initially 832 * requested. 833 */ 834 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); 835 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); 836 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); 837 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); 838 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); 839 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); 840 841 i2c_register_board_info(0, db1200_i2c_devs, 842 ARRAY_SIZE(db1200_i2c_devs)); 843 spi_register_board_info(db1200_spi_devs, 844 ARRAY_SIZE(db1200_i2c_devs)); 845 846 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 847 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 848 * or S12 on the PB1200. 849 */ 850 851 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 852 * this pin is claimed by PSC0 (unused though, but pinmux doesn't 853 * allow to free it without crippling the SPI interface). 854 * As a result, in SPI mode, OTG simply won't work (PSC0 uses 855 * it as an input pin which is pulled high on the boards). 856 */ 857 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A; 858 859 /* switch off OTG VBUS supply */ 860 gpio_request(215, "otg-vbus"); 861 gpio_direction_output(215, 1); 862 863 printk(KERN_INFO "%s device configuration:\n", get_system_type()); 864 865 sw = bcsr_read(BCSR_SWITCHES); 866 if (sw & BCSR_SWITCHES_DIP_8) { 867 db1200_devs[0] = &db1200_i2c_dev; 868 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); 869 870 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ 871 872 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); 873 printk(KERN_INFO " OTG port VBUS supply available!\n"); 874 } else { 875 db1200_devs[0] = &db1200_spi_dev; 876 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); 877 878 pfc |= (1 << 17); /* PSC0 owns GPIO215 */ 879 880 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); 881 printk(KERN_INFO " OTG port VBUS supply disabled\n"); 882 } 883 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 884 885 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! 886 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S 887 */ 888 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; 889 if (sw == BCSR_SWITCHES_DIP_8) { 890 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); 891 db1200_audio_dev.name = "au1xpsc_i2s"; 892 db1200_sound_dev.name = "db1200-i2s"; 893 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); 894 } else { 895 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); 896 db1200_audio_dev.name = "au1xpsc_ac97"; 897 db1200_sound_dev.name = "db1200-ac97"; 898 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); 899 } 900 901 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 902 __raw_writel(PSC_SEL_CLK_SERCLK, 903 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 904 wmb(); 905 906 db1x_register_pcmcia_socket( 907 AU1000_PCMCIA_ATTR_PHYS_ADDR, 908 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 909 AU1000_PCMCIA_MEM_PHYS_ADDR, 910 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 911 AU1000_PCMCIA_IO_PHYS_ADDR, 912 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 913 DB1200_PC0_INT, DB1200_PC0_INSERT_INT, 914 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); 915 916 db1x_register_pcmcia_socket( 917 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 918 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 919 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 920 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 921 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 922 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 923 DB1200_PC1_INT, DB1200_PC1_INSERT_INT, 924 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); 925 926 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 927 db1x_register_norflash(64 << 20, 2, swapped); 928 929 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 930 931 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ 932 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 933 (bid == BCSR_WHOAMI_PB1200_DDR2)) 934 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); 935 936 return 0; 937 } 938