1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DBAu1000/1500/1100 PBAu1100/1500 board support 4 * 5 * Copyright 2000, 2008 MontaVista Software Inc. 6 * Author: MontaVista Software, Inc. <source@mvista.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/gpio.h> 12 #include <linux/gpio/machine.h> 13 #include <linux/gpio/property.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/leds.h> 17 #include <linux/mmc/host.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/pm.h> 21 #include <linux/spi/spi.h> 22 #include <asm/mach-au1x00/au1000.h> 23 #include <asm/mach-au1x00/gpio-au1000.h> 24 #include <asm/mach-au1x00/au1000_dma.h> 25 #include <asm/mach-au1x00/au1100_mmc.h> 26 #include <asm/mach-db1x00/bcsr.h> 27 #include <asm/reboot.h> 28 #include <prom.h> 29 30 #include "db1xxx.h" 31 #include "platform.h" 32 33 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) 34 35 const char *get_system_type(void); 36 37 int __init db1000_board_setup(void) 38 { 39 /* initialize board register space */ 40 bcsr_init(DB1000_BCSR_PHYS_ADDR, 41 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); 42 43 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { 44 case BCSR_WHOAMI_DB1000: 45 case BCSR_WHOAMI_DB1500: 46 case BCSR_WHOAMI_DB1100: 47 case BCSR_WHOAMI_PB1500: 48 case BCSR_WHOAMI_PB1500R2: 49 case BCSR_WHOAMI_PB1100: 50 pr_info("AMD Alchemy %s Board\n", get_system_type()); 51 return 0; 52 } 53 return -ENODEV; 54 } 55 56 static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) 57 { 58 if ((slot < 12) || (slot > 13) || pin == 0) 59 return -1; 60 if (slot == 12) 61 return (pin == 1) ? AU1500_PCI_INTA : 0xff; 62 if (slot == 13) { 63 switch (pin) { 64 case 1: return AU1500_PCI_INTA; 65 case 2: return AU1500_PCI_INTB; 66 case 3: return AU1500_PCI_INTC; 67 case 4: return AU1500_PCI_INTD; 68 } 69 } 70 return -1; 71 } 72 73 static u64 au1xxx_all_dmamask = DMA_BIT_MASK(32); 74 75 static struct resource alchemy_pci_host_res[] = { 76 [0] = { 77 .start = AU1500_PCI_PHYS_ADDR, 78 .end = AU1500_PCI_PHYS_ADDR + 0xfff, 79 .flags = IORESOURCE_MEM, 80 }, 81 }; 82 83 static struct alchemy_pci_platdata db1500_pci_pd = { 84 .board_map_irq = db1500_map_pci_irq, 85 }; 86 87 static struct platform_device db1500_pci_host_dev = { 88 .dev.platform_data = &db1500_pci_pd, 89 .name = "alchemy-pci", 90 .id = 0, 91 .num_resources = ARRAY_SIZE(alchemy_pci_host_res), 92 .resource = alchemy_pci_host_res, 93 }; 94 95 int __init db1500_pci_setup(void) 96 { 97 return platform_device_register(&db1500_pci_host_dev); 98 } 99 100 static struct resource au1100_lcd_resources[] = { 101 [0] = { 102 .start = AU1100_LCD_PHYS_ADDR, 103 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, 104 .flags = IORESOURCE_MEM, 105 }, 106 [1] = { 107 .start = AU1100_LCD_INT, 108 .end = AU1100_LCD_INT, 109 .flags = IORESOURCE_IRQ, 110 } 111 }; 112 113 static struct platform_device au1100_lcd_device = { 114 .name = "au1100-lcd", 115 .id = 0, 116 .dev = { 117 .dma_mask = &au1xxx_all_dmamask, 118 .coherent_dma_mask = DMA_BIT_MASK(32), 119 }, 120 .num_resources = ARRAY_SIZE(au1100_lcd_resources), 121 .resource = au1100_lcd_resources, 122 }; 123 124 static struct resource alchemy_ac97c_res[] = { 125 [0] = { 126 .start = AU1000_AC97_PHYS_ADDR, 127 .end = AU1000_AC97_PHYS_ADDR + 0xfff, 128 .flags = IORESOURCE_MEM, 129 }, 130 [1] = { 131 .start = DMA_ID_AC97C_TX, 132 .end = DMA_ID_AC97C_TX, 133 .flags = IORESOURCE_DMA, 134 }, 135 [2] = { 136 .start = DMA_ID_AC97C_RX, 137 .end = DMA_ID_AC97C_RX, 138 .flags = IORESOURCE_DMA, 139 }, 140 }; 141 142 static struct platform_device alchemy_ac97c_dev = { 143 .name = "alchemy-ac97c", 144 .id = -1, 145 .resource = alchemy_ac97c_res, 146 .num_resources = ARRAY_SIZE(alchemy_ac97c_res), 147 }; 148 149 static struct platform_device alchemy_ac97c_dma_dev = { 150 .name = "alchemy-pcm-dma", 151 .id = 0, 152 }; 153 154 static struct platform_device db1x00_codec_dev = { 155 .name = "ac97-codec", 156 .id = -1, 157 }; 158 159 static struct platform_device db1x00_audio_dev = { 160 .name = "db1000-audio", 161 .dev = { 162 .dma_mask = &au1xxx_all_dmamask, 163 .coherent_dma_mask = DMA_BIT_MASK(32), 164 }, 165 }; 166 167 /******************************************************************************/ 168 169 #ifdef CONFIG_MMC_AU1X 170 static irqreturn_t db1100_mmc_cd(int irq, void *ptr) 171 { 172 mmc_detect_change(ptr, msecs_to_jiffies(500)); 173 return IRQ_HANDLED; 174 } 175 176 static int db1100_mmc_cd_setup(void *mmc_host, int en) 177 { 178 int ret = 0, irq; 179 180 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) 181 irq = AU1100_GPIO19_INT; 182 else 183 irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */ 184 185 if (en) { 186 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH); 187 ret = request_irq(irq, db1100_mmc_cd, 0, 188 "sd0_cd", mmc_host); 189 } else 190 free_irq(irq, mmc_host); 191 return ret; 192 } 193 194 static int db1100_mmc1_cd_setup(void *mmc_host, int en) 195 { 196 int ret = 0, irq; 197 198 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) 199 irq = AU1100_GPIO20_INT; 200 else 201 irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */ 202 203 if (en) { 204 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH); 205 ret = request_irq(irq, db1100_mmc_cd, 0, 206 "sd1_cd", mmc_host); 207 } else 208 free_irq(irq, mmc_host); 209 return ret; 210 } 211 212 static int db1100_mmc_card_readonly(void *mmc_host) 213 { 214 /* testing suggests that this bit is inverted */ 215 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1; 216 } 217 218 static int db1100_mmc_card_inserted(void *mmc_host) 219 { 220 return !alchemy_gpio_get_value(19); 221 } 222 223 static void db1100_mmc_set_power(void *mmc_host, int state) 224 { 225 int bit; 226 227 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) 228 bit = BCSR_BOARD_SD0PWR; 229 else 230 bit = BCSR_BOARD_PB1100_SD0PWR; 231 232 if (state) { 233 bcsr_mod(BCSR_BOARD, 0, bit); 234 msleep(400); /* stabilization time */ 235 } else 236 bcsr_mod(BCSR_BOARD, bit, 0); 237 } 238 239 static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b) 240 { 241 if (b != LED_OFF) 242 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 243 else 244 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 245 } 246 247 static struct led_classdev db1100_mmc_led = { 248 .brightness_set = db1100_mmcled_set, 249 }; 250 251 static int db1100_mmc1_card_readonly(void *mmc_host) 252 { 253 return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0; 254 } 255 256 static int db1100_mmc1_card_inserted(void *mmc_host) 257 { 258 return !alchemy_gpio_get_value(20); 259 } 260 261 static void db1100_mmc1_set_power(void *mmc_host, int state) 262 { 263 int bit; 264 265 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) 266 bit = BCSR_BOARD_SD1PWR; 267 else 268 bit = BCSR_BOARD_PB1100_SD1PWR; 269 270 if (state) { 271 bcsr_mod(BCSR_BOARD, 0, bit); 272 msleep(400); /* stabilization time */ 273 } else 274 bcsr_mod(BCSR_BOARD, bit, 0); 275 } 276 277 static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b) 278 { 279 if (b != LED_OFF) 280 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 281 else 282 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 283 } 284 285 static struct led_classdev db1100_mmc1_led = { 286 .brightness_set = db1100_mmc1led_set, 287 }; 288 289 static struct au1xmmc_platform_data db1100_mmc_platdata[2] = { 290 [0] = { 291 .cd_setup = db1100_mmc_cd_setup, 292 .set_power = db1100_mmc_set_power, 293 .card_inserted = db1100_mmc_card_inserted, 294 .card_readonly = db1100_mmc_card_readonly, 295 .led = &db1100_mmc_led, 296 }, 297 [1] = { 298 .cd_setup = db1100_mmc1_cd_setup, 299 .set_power = db1100_mmc1_set_power, 300 .card_inserted = db1100_mmc1_card_inserted, 301 .card_readonly = db1100_mmc1_card_readonly, 302 .led = &db1100_mmc1_led, 303 }, 304 }; 305 306 static struct resource au1100_mmc0_resources[] = { 307 [0] = { 308 .start = AU1100_SD0_PHYS_ADDR, 309 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 310 .flags = IORESOURCE_MEM, 311 }, 312 [1] = { 313 .start = AU1100_SD_INT, 314 .end = AU1100_SD_INT, 315 .flags = IORESOURCE_IRQ, 316 }, 317 [2] = { 318 .start = DMA_ID_SD0_TX, 319 .end = DMA_ID_SD0_TX, 320 .flags = IORESOURCE_DMA, 321 }, 322 [3] = { 323 .start = DMA_ID_SD0_RX, 324 .end = DMA_ID_SD0_RX, 325 .flags = IORESOURCE_DMA, 326 } 327 }; 328 329 static struct platform_device db1100_mmc0_dev = { 330 .name = "au1xxx-mmc", 331 .id = 0, 332 .dev = { 333 .dma_mask = &au1xxx_all_dmamask, 334 .coherent_dma_mask = DMA_BIT_MASK(32), 335 .platform_data = &db1100_mmc_platdata[0], 336 }, 337 .num_resources = ARRAY_SIZE(au1100_mmc0_resources), 338 .resource = au1100_mmc0_resources, 339 }; 340 341 static struct resource au1100_mmc1_res[] = { 342 [0] = { 343 .start = AU1100_SD1_PHYS_ADDR, 344 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 345 .flags = IORESOURCE_MEM, 346 }, 347 [1] = { 348 .start = AU1100_SD_INT, 349 .end = AU1100_SD_INT, 350 .flags = IORESOURCE_IRQ, 351 }, 352 [2] = { 353 .start = DMA_ID_SD1_TX, 354 .end = DMA_ID_SD1_TX, 355 .flags = IORESOURCE_DMA, 356 }, 357 [3] = { 358 .start = DMA_ID_SD1_RX, 359 .end = DMA_ID_SD1_RX, 360 .flags = IORESOURCE_DMA, 361 } 362 }; 363 364 static struct platform_device db1100_mmc1_dev = { 365 .name = "au1xxx-mmc", 366 .id = 1, 367 .dev = { 368 .dma_mask = &au1xxx_all_dmamask, 369 .coherent_dma_mask = DMA_BIT_MASK(32), 370 .platform_data = &db1100_mmc_platdata[1], 371 }, 372 .num_resources = ARRAY_SIZE(au1100_mmc1_res), 373 .resource = au1100_mmc1_res, 374 }; 375 #endif /* CONFIG_MMC_AU1X */ 376 377 /******************************************************************************/ 378 379 static const struct property_entry db1100_ads7846_props[] = { 380 PROPERTY_ENTRY_U16("ti,vref_min", 3300), 381 PROPERTY_ENTRY_GPIO("pendown-gpios", &alchemy_gpio2_node, 21, GPIO_ACTIVE_LOW), 382 { } 383 }; 384 385 static const struct software_node db1100_ads7846_swnode = { 386 .name = "ads7846", 387 .properties = db1100_ads7846_props, 388 }; 389 390 static struct spi_board_info db1100_spi_info[] __initdata = { 391 [0] = { 392 .modalias = "ads7846", 393 .max_speed_hz = 3250000, 394 .bus_num = 0, 395 .chip_select = 0, 396 .mode = 0, 397 .irq = AU1100_GPIO21_INT, 398 .swnode = &db1100_ads7846_swnode, 399 }, 400 }; 401 402 /* 403 * Alchemy GPIO 2 has its base at 200 so the GPIO lines 404 * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip. 405 */ 406 static const struct property_entry db1100_spi_dev_properties[] __initconst = { 407 PROPERTY_ENTRY_GPIO("miso-gpios", 408 &alchemy_gpio2_node, 7, GPIO_ACTIVE_HIGH), 409 PROPERTY_ENTRY_GPIO("mosi-gpios", 410 &alchemy_gpio2_node, 8, GPIO_ACTIVE_HIGH), 411 PROPERTY_ENTRY_GPIO("sck-gpios", 412 &alchemy_gpio2_node, 9, GPIO_ACTIVE_HIGH), 413 PROPERTY_ENTRY_GPIO("cs-gpios", 414 &alchemy_gpio2_node, 10, GPIO_ACTIVE_HIGH), 415 { } 416 }; 417 418 static const struct platform_device_info db1100_spi_dev_info __initconst = { 419 .name = "spi_gpio", 420 .id = 0, 421 .dma_mask = DMA_BIT_MASK(32), 422 .properties = db1100_spi_dev_properties, 423 }; 424 425 static struct platform_device *db1x00_devs[] = { 426 &db1x00_codec_dev, 427 &alchemy_ac97c_dma_dev, 428 &alchemy_ac97c_dev, 429 &db1x00_audio_dev, 430 }; 431 432 static struct platform_device *db1100_devs[] = { 433 &au1100_lcd_device, 434 #ifdef CONFIG_MMC_AU1X 435 &db1100_mmc0_dev, 436 &db1100_mmc1_dev, 437 #endif 438 }; 439 440 int __init db1000_dev_setup(void) 441 { 442 int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 443 int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; 444 int err; 445 unsigned long pfc; 446 struct clk *c, *p; 447 struct platform_device *spi_dev; 448 449 if (board == BCSR_WHOAMI_DB1500) { 450 c0 = AU1500_GPIO2_INT; 451 c1 = AU1500_GPIO5_INT; 452 d0 = 0; /* GPIO number, NOT irq! */ 453 d1 = 3; /* GPIO number, NOT irq! */ 454 s0 = AU1500_GPIO1_INT; 455 s1 = AU1500_GPIO4_INT; 456 } else if (board == BCSR_WHOAMI_DB1100) { 457 c0 = AU1100_GPIO2_INT; 458 c1 = AU1100_GPIO5_INT; 459 d0 = 0; /* GPIO number, NOT irq! */ 460 d1 = 3; /* GPIO number, NOT irq! */ 461 s0 = AU1100_GPIO1_INT; 462 s1 = AU1100_GPIO4_INT; 463 464 gpio_request(19, "sd0_cd"); 465 gpio_request(20, "sd1_cd"); 466 gpio_direction_input(19); /* sd0 cd# */ 467 gpio_direction_input(20); /* sd1 cd# */ 468 469 /* spi_gpio on SSI0 pins */ 470 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC); 471 pfc |= (1 << 0); /* SSI0 pins as GPIOs */ 472 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 473 474 spi_register_board_info(db1100_spi_info, 475 ARRAY_SIZE(db1100_spi_info)); 476 477 /* link LCD clock to AUXPLL */ 478 p = clk_get(NULL, "auxpll_clk"); 479 c = clk_get(NULL, "lcd_intclk"); 480 if (!IS_ERR(c) && !IS_ERR(p)) { 481 clk_set_parent(c, p); 482 clk_set_rate(c, clk_get_rate(p)); 483 } 484 if (!IS_ERR(c)) 485 clk_put(c); 486 if (!IS_ERR(p)) 487 clk_put(p); 488 489 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); 490 491 spi_dev = platform_device_register_full(&db1100_spi_dev_info); 492 err = PTR_ERR_OR_ZERO(spi_dev); 493 if (err) 494 pr_err("failed to register SPI controller: %d\n", err); 495 } else if (board == BCSR_WHOAMI_DB1000) { 496 c0 = AU1000_GPIO2_INT; 497 c1 = AU1000_GPIO5_INT; 498 d0 = 0; /* GPIO number, NOT irq! */ 499 d1 = 3; /* GPIO number, NOT irq! */ 500 s0 = AU1000_GPIO1_INT; 501 s1 = AU1000_GPIO4_INT; 502 } else if ((board == BCSR_WHOAMI_PB1500) || 503 (board == BCSR_WHOAMI_PB1500R2)) { 504 c0 = AU1500_GPIO203_INT; 505 d0 = 1; /* GPIO number, NOT irq! */ 506 s0 = AU1500_GPIO202_INT; 507 twosocks = 0; 508 flashsize = 64; 509 /* RTC and daughtercard irqs */ 510 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW); 511 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); 512 /* EPSON S1D13806 0x1b000000 513 * SRAM 1MB/2MB 0x1a000000 514 * DS1693 RTC 0x0c000000 515 */ 516 } else if (board == BCSR_WHOAMI_PB1100) { 517 c0 = AU1100_GPIO11_INT; 518 d0 = 9; /* GPIO number, NOT irq! */ 519 s0 = AU1100_GPIO10_INT; 520 twosocks = 0; 521 flashsize = 64; 522 /* pendown, rtc, daughtercard irqs */ 523 irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW); 524 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW); 525 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW); 526 /* EPSON S1D13806 0x1b000000 527 * SRAM 1MB/2MB 0x1a000000 528 * DiskOnChip 0x0d000000 529 * DS1693 RTC 0x0c000000 530 */ 531 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); 532 } else 533 return 0; /* unknown board, no further dev setup to do */ 534 535 irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); 536 irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); 537 538 db1x_register_pcmcia_socket( 539 AU1000_PCMCIA_ATTR_PHYS_ADDR, 540 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 541 AU1000_PCMCIA_MEM_PHYS_ADDR, 542 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 543 AU1000_PCMCIA_IO_PHYS_ADDR, 544 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 545 c0, d0, /*s0*/0, 0, 0); 546 547 if (twosocks) { 548 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); 549 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); 550 551 db1x_register_pcmcia_socket( 552 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 553 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 554 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 555 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 556 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 557 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 558 c1, d1, /*s1*/0, 0, 1); 559 } 560 561 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); 562 db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED); 563 return 0; 564 } 565