1 /* 2 * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com> 3 * 4 * Previous incarnations were: 5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> 6 * Copied and modified Carsten Langgaard's time.c 7 * 8 * Carsten Langgaard, carstenl@mips.com 9 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 10 * 11 * ######################################################################## 12 * 13 * This program is free software; you can distribute it and/or modify it 14 * under the terms of the GNU General Public License (Version 2) as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 20 * for more details. 21 * 22 * You should have received a copy of the GNU General Public License along 23 * with this program; if not, write to the Free Software Foundation, Inc., 24 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 25 * 26 * ######################################################################## 27 * 28 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the 29 * databooks). Firmware/Board init code must enable the counters in the 30 * counter control register, otherwise the CP0 counter clocksource/event 31 * will be installed instead (and use of 'wait' instruction is prohibited). 32 */ 33 34 #include <linux/clockchips.h> 35 #include <linux/clocksource.h> 36 #include <linux/interrupt.h> 37 #include <linux/spinlock.h> 38 39 #include <asm/idle.h> 40 #include <asm/processor.h> 41 #include <asm/time.h> 42 #include <asm/mach-au1x00/au1000.h> 43 44 /* 32kHz clock enabled and detected */ 45 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) 46 47 static cycle_t au1x_counter1_read(struct clocksource *cs) 48 { 49 return alchemy_rdsys(AU1000_SYS_RTCREAD); 50 } 51 52 static struct clocksource au1x_counter1_clocksource = { 53 .name = "alchemy-counter1", 54 .read = au1x_counter1_read, 55 .mask = CLOCKSOURCE_MASK(32), 56 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 57 .rating = 1500, 58 }; 59 60 static int au1x_rtcmatch2_set_next_event(unsigned long delta, 61 struct clock_event_device *cd) 62 { 63 delta += alchemy_rdsys(AU1000_SYS_RTCREAD); 64 /* wait for register access */ 65 while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21) 66 ; 67 alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2); 68 69 return 0; 70 } 71 72 static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode, 73 struct clock_event_device *cd) 74 { 75 } 76 77 static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) 78 { 79 struct clock_event_device *cd = dev_id; 80 cd->event_handler(cd); 81 return IRQ_HANDLED; 82 } 83 84 static struct clock_event_device au1x_rtcmatch2_clockdev = { 85 .name = "rtcmatch2", 86 .features = CLOCK_EVT_FEAT_ONESHOT, 87 .rating = 1500, 88 .set_next_event = au1x_rtcmatch2_set_next_event, 89 .set_mode = au1x_rtcmatch2_set_mode, 90 .cpumask = cpu_all_mask, 91 }; 92 93 static struct irqaction au1x_rtcmatch2_irqaction = { 94 .handler = au1x_rtcmatch2_irq, 95 .flags = IRQF_TIMER, 96 .name = "timer", 97 .dev_id = &au1x_rtcmatch2_clockdev, 98 }; 99 100 static int __init alchemy_time_init(unsigned int m2int) 101 { 102 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; 103 unsigned long t; 104 105 au1x_rtcmatch2_clockdev.irq = m2int; 106 107 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock 108 * has been detected. If so install the rtcmatch2 clocksource, 109 * otherwise don't bother. Note that both bits being set is by 110 * no means a definite guarantee that the counters actually work 111 * (the 32S bit seems to be stuck set to 1 once a single clock- 112 * edge is detected, hence the timeouts). 113 */ 114 if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK)) 115 goto cntr_err; 116 117 /* 118 * setup counter 1 (RTC) to tick at full speed 119 */ 120 t = 0xffffff; 121 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t) 122 asm volatile ("nop"); 123 if (!t) 124 goto cntr_err; 125 126 alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */ 127 128 t = 0xffffff; 129 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t) 130 asm volatile ("nop"); 131 if (!t) 132 goto cntr_err; 133 alchemy_wrsys(0, AU1000_SYS_RTCWRITE); 134 135 t = 0xffffff; 136 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t) 137 asm volatile ("nop"); 138 if (!t) 139 goto cntr_err; 140 141 /* register counter1 clocksource and event device */ 142 clocksource_register_hz(&au1x_counter1_clocksource, 32768); 143 144 cd->shift = 32; 145 cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift); 146 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); 147 cd->min_delta_ns = clockevent_delta2ns(9, cd); /* ~0.28ms */ 148 clockevents_register_device(cd); 149 setup_irq(m2int, &au1x_rtcmatch2_irqaction); 150 151 printk(KERN_INFO "Alchemy clocksource installed\n"); 152 153 return 0; 154 155 cntr_err: 156 return -1; 157 } 158 159 static int alchemy_m2inttab[] __initdata = { 160 AU1000_RTC_MATCH2_INT, 161 AU1500_RTC_MATCH2_INT, 162 AU1100_RTC_MATCH2_INT, 163 AU1550_RTC_MATCH2_INT, 164 AU1200_RTC_MATCH2_INT, 165 AU1300_RTC_MATCH2_INT, 166 }; 167 168 void __init plat_time_init(void) 169 { 170 int t; 171 172 t = alchemy_get_cputype(); 173 if (t == ALCHEMY_CPU_UNKNOWN || 174 alchemy_time_init(alchemy_m2inttab[t])) 175 cpu_wait = NULL; /* wait doesn't work with r4k timer */ 176 } 177