1 /* 2 * BRIEF MODULE DESCRIPTION 3 * Au1xx0 Power Management routines. 4 * 5 * Copyright 2001, 2008 MontaVista Software Inc. 6 * Author: MontaVista Software, Inc. <source@mvista.com> 7 * 8 * Some of the routines are right out of init/main.c, whose 9 * copyrights apply here. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/pm.h> 34 #include <linux/sysctl.h> 35 #include <linux/jiffies.h> 36 37 #include <asm/uaccess.h> 38 #include <asm/mach-au1x00/au1000.h> 39 40 #ifdef CONFIG_PM 41 42 /* 43 * We need to save/restore a bunch of core registers that are 44 * either volatile or reset to some state across a processor sleep. 45 * If reading a register doesn't provide a proper result for a 46 * later restore, we have to provide a function for loading that 47 * register and save a copy. 48 * 49 * We only have to save/restore registers that aren't otherwise 50 * done as part of a driver pm_* function. 51 */ 52 static unsigned int sleep_uart0_inten; 53 static unsigned int sleep_uart0_fifoctl; 54 static unsigned int sleep_uart0_linectl; 55 static unsigned int sleep_uart0_clkdiv; 56 static unsigned int sleep_uart0_enable; 57 static unsigned int sleep_usb[2]; 58 static unsigned int sleep_sys_clocks[5]; 59 static unsigned int sleep_sys_pinfunc; 60 static unsigned int sleep_static_memctlr[4][3]; 61 62 63 static void save_core_regs(void) 64 { 65 extern void save_au1xxx_intctl(void); 66 extern void pm_eth0_shutdown(void); 67 68 /* 69 * Do the serial ports.....these really should be a pm_* 70 * registered function by the driver......but of course the 71 * standard serial driver doesn't understand our Au1xxx 72 * unique registers. 73 */ 74 sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER); 75 sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR); 76 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); 77 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); 78 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); 79 au_sync(); 80 81 #ifndef CONFIG_SOC_AU1200 82 /* Shutdown USB host/device. */ 83 sleep_usb[0] = au_readl(USB_HOST_CONFIG); 84 85 /* There appears to be some undocumented reset register.... */ 86 au_writel(0, 0xb0100004); 87 au_sync(); 88 au_writel(0, USB_HOST_CONFIG); 89 au_sync(); 90 91 sleep_usb[1] = au_readl(USBD_ENABLE); 92 au_writel(0, USBD_ENABLE); 93 au_sync(); 94 95 #else /* AU1200 */ 96 97 /* enable access to OTG mmio so we can save OTG CAP/MUX. 98 * FIXME: write an OTG driver and move this stuff there! 99 */ 100 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); 101 au_sync(); 102 sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ 103 sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ 104 #endif 105 106 /* Clocks and PLLs. */ 107 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); 108 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); 109 sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); 110 sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); 111 sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); 112 113 /* pin mux config */ 114 sleep_sys_pinfunc = au_readl(SYS_PINFUNC); 115 116 /* Save the static memory controller configuration. */ 117 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); 118 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); 119 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); 120 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1); 121 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1); 122 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1); 123 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2); 124 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2); 125 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2); 126 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); 127 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); 128 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); 129 } 130 131 static void restore_core_regs(void) 132 { 133 /* restore clock configuration. Writing CPUPLL last will 134 * stall a bit and stabilize other clocks (unless this is 135 * one of those Au1000 with a write-only PLL, where we dont 136 * have a valid value) 137 */ 138 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); 139 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); 140 au_writel(sleep_sys_clocks[2], SYS_CLKSRC); 141 au_writel(sleep_sys_clocks[4], SYS_AUXPLL); 142 if (!au1xxx_cpu_has_pll_wo()) 143 au_writel(sleep_sys_clocks[3], SYS_CPUPLL); 144 au_sync(); 145 146 au_writel(sleep_sys_pinfunc, SYS_PINFUNC); 147 au_sync(); 148 149 #ifndef CONFIG_SOC_AU1200 150 au_writel(sleep_usb[0], USB_HOST_CONFIG); 151 au_writel(sleep_usb[1], USBD_ENABLE); 152 au_sync(); 153 #else 154 /* enable accces to OTG memory */ 155 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); 156 au_sync(); 157 158 /* restore OTG caps and port mux. */ 159 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ 160 au_sync(); 161 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ 162 au_sync(); 163 #endif 164 165 /* Restore the static memory controller configuration. */ 166 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); 167 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); 168 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); 169 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); 170 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); 171 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); 172 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); 173 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); 174 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); 175 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); 176 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); 177 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); 178 179 /* 180 * Enable the UART if it was enabled before sleep. 181 * I guess I should define module control bits........ 182 */ 183 if (sleep_uart0_enable & 0x02) { 184 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 185 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 186 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 187 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync(); 188 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync(); 189 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); 190 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); 191 } 192 } 193 194 void au_sleep(void) 195 { 196 int cpuid = alchemy_get_cputype(); 197 if (cpuid != ALCHEMY_CPU_UNKNOWN) { 198 save_core_regs(); 199 if (cpuid <= ALCHEMY_CPU_AU1500) 200 alchemy_sleep_au1000(); 201 else if (cpuid <= ALCHEMY_CPU_AU1200) 202 alchemy_sleep_au1550(); 203 restore_core_regs(); 204 } 205 } 206 207 #endif /* CONFIG_PM */ 208