1 /* 2 * BRIEF MODULE DESCRIPTION 3 * Au1xx0 Power Management routines. 4 * 5 * Copyright 2001, 2008 MontaVista Software Inc. 6 * Author: MontaVista Software, Inc. <source@mvista.com> 7 * 8 * Some of the routines are right out of init/main.c, whose 9 * copyrights apply here. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/pm.h> 34 #include <linux/sysctl.h> 35 #include <linux/jiffies.h> 36 37 #include <asm/uaccess.h> 38 #include <asm/cacheflush.h> 39 #include <asm/mach-au1x00/au1000.h> 40 41 #ifdef CONFIG_PM 42 43 #define DEBUG 1 44 #ifdef DEBUG 45 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args) 46 #else 47 #define DPRINTK(fmt, args...) 48 #endif 49 50 static void au1000_calibrate_delay(void); 51 52 extern unsigned long save_local_and_disable(int controller); 53 extern void restore_local_and_enable(int controller, unsigned long mask); 54 55 static DEFINE_SPINLOCK(pm_lock); 56 57 /* 58 * We need to save/restore a bunch of core registers that are 59 * either volatile or reset to some state across a processor sleep. 60 * If reading a register doesn't provide a proper result for a 61 * later restore, we have to provide a function for loading that 62 * register and save a copy. 63 * 64 * We only have to save/restore registers that aren't otherwise 65 * done as part of a driver pm_* function. 66 */ 67 static unsigned int sleep_aux_pll_cntrl; 68 static unsigned int sleep_cpu_pll_cntrl; 69 static unsigned int sleep_pin_function; 70 static unsigned int sleep_uart0_inten; 71 static unsigned int sleep_uart0_fifoctl; 72 static unsigned int sleep_uart0_linectl; 73 static unsigned int sleep_uart0_clkdiv; 74 static unsigned int sleep_uart0_enable; 75 static unsigned int sleep_usbhost_enable; 76 static unsigned int sleep_usbdev_enable; 77 static unsigned int sleep_static_memctlr[4][3]; 78 79 /* 80 * Define this to cause the value you write to /proc/sys/pm/sleep to 81 * set the TOY timer for the amount of time you want to sleep. 82 * This is done mainly for testing, but may be useful in other cases. 83 * The value is number of 32KHz ticks to sleep. 84 */ 85 #define SLEEP_TEST_TIMEOUT 1 86 #ifdef SLEEP_TEST_TIMEOUT 87 static int sleep_ticks; 88 void wakeup_counter0_set(int ticks); 89 #endif 90 91 static void save_core_regs(void) 92 { 93 extern void save_au1xxx_intctl(void); 94 extern void pm_eth0_shutdown(void); 95 96 /* 97 * Do the serial ports.....these really should be a pm_* 98 * registered function by the driver......but of course the 99 * standard serial driver doesn't understand our Au1xxx 100 * unique registers. 101 */ 102 sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER); 103 sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR); 104 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); 105 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); 106 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); 107 108 /* Shutdown USB host/device. */ 109 sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); 110 111 /* There appears to be some undocumented reset register.... */ 112 au_writel(0, 0xb0100004); au_sync(); 113 au_writel(0, USB_HOST_CONFIG); au_sync(); 114 115 sleep_usbdev_enable = au_readl(USBD_ENABLE); 116 au_writel(0, USBD_ENABLE); au_sync(); 117 118 /* Save interrupt controller state. */ 119 save_au1xxx_intctl(); 120 121 /* Clocks and PLLs. */ 122 sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); 123 124 /* 125 * We don't really need to do this one, but unless we 126 * write it again it won't have a valid value if we 127 * happen to read it. 128 */ 129 sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL); 130 131 sleep_pin_function = au_readl(SYS_PINFUNC); 132 133 /* Save the static memory controller configuration. */ 134 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); 135 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); 136 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); 137 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1); 138 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1); 139 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1); 140 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2); 141 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2); 142 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2); 143 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); 144 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); 145 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); 146 } 147 148 static void restore_core_regs(void) 149 { 150 extern void restore_au1xxx_intctl(void); 151 extern void wakeup_counter0_adjust(void); 152 153 au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync(); 154 au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); 155 au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); 156 157 /* Restore the static memory controller configuration. */ 158 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); 159 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); 160 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); 161 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); 162 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); 163 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); 164 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); 165 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); 166 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); 167 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); 168 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); 169 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); 170 171 /* 172 * Enable the UART if it was enabled before sleep. 173 * I guess I should define module control bits........ 174 */ 175 if (sleep_uart0_enable & 0x02) { 176 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 177 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 178 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 179 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync(); 180 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync(); 181 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); 182 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); 183 } 184 185 restore_au1xxx_intctl(); 186 wakeup_counter0_adjust(); 187 } 188 189 unsigned long suspend_mode; 190 191 void wakeup_from_suspend(void) 192 { 193 suspend_mode = 0; 194 } 195 196 int au_sleep(void) 197 { 198 unsigned long wakeup, flags; 199 extern void save_and_sleep(void); 200 201 spin_lock_irqsave(&pm_lock, flags); 202 203 save_core_regs(); 204 205 flush_cache_all(); 206 207 /** 208 ** The code below is all system dependent and we should probably 209 ** have a function call out of here to set this up. You need 210 ** to configure the GPIO or timer interrupts that will bring 211 ** you out of sleep. 212 ** For testing, the TOY counter wakeup is useful. 213 **/ 214 #if 0 215 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); 216 217 /* GPIO 6 can cause a wake up event */ 218 wakeup = au_readl(SYS_WAKEMSK); 219 wakeup &= ~(1 << 8); /* turn off match20 wakeup */ 220 wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */ 221 #else 222 /* For testing, allow match20 to wake us up. */ 223 #ifdef SLEEP_TEST_TIMEOUT 224 wakeup_counter0_set(sleep_ticks); 225 #endif 226 wakeup = 1 << 8; /* turn on match20 wakeup */ 227 wakeup = 0; 228 #endif 229 au_writel(1, SYS_WAKESRC); /* clear cause */ 230 au_sync(); 231 au_writel(wakeup, SYS_WAKEMSK); 232 au_sync(); 233 234 save_and_sleep(); 235 236 /* 237 * After a wakeup, the cpu vectors back to 0x1fc00000, so 238 * it's up to the boot code to get us back here. 239 */ 240 restore_core_regs(); 241 spin_unlock_irqrestore(&pm_lock, flags); 242 return 0; 243 } 244 245 static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, 246 void __user *buffer, size_t *len, loff_t *ppos) 247 { 248 #ifdef SLEEP_TEST_TIMEOUT 249 #define TMPBUFLEN2 16 250 char buf[TMPBUFLEN2], *p; 251 #endif 252 253 if (!write) 254 *len = 0; 255 else { 256 #ifdef SLEEP_TEST_TIMEOUT 257 if (*len > TMPBUFLEN2 - 1) 258 return -EFAULT; 259 if (copy_from_user(buf, buffer, *len)) 260 return -EFAULT; 261 buf[*len] = 0; 262 p = buf; 263 sleep_ticks = simple_strtoul(p, &p, 0); 264 #endif 265 266 au_sleep(); 267 } 268 return 0; 269 } 270 271 static int pm_do_freq(ctl_table *ctl, int write, struct file *file, 272 void __user *buffer, size_t *len, loff_t *ppos) 273 { 274 int retval = 0, i; 275 unsigned long val, pll; 276 #define TMPBUFLEN 64 277 #define MAX_CPU_FREQ 396 278 char buf[TMPBUFLEN], *p; 279 unsigned long flags, intc0_mask, intc1_mask; 280 unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh; 281 unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; 282 unsigned long baud_rate; 283 284 spin_lock_irqsave(&pm_lock, flags); 285 if (!write) 286 *len = 0; 287 else { 288 /* Parse the new frequency */ 289 if (*len > TMPBUFLEN - 1) { 290 spin_unlock_irqrestore(&pm_lock, flags); 291 return -EFAULT; 292 } 293 if (copy_from_user(buf, buffer, *len)) { 294 spin_unlock_irqrestore(&pm_lock, flags); 295 return -EFAULT; 296 } 297 buf[*len] = 0; 298 p = buf; 299 val = simple_strtoul(p, &p, 0); 300 if (val > MAX_CPU_FREQ) { 301 spin_unlock_irqrestore(&pm_lock, flags); 302 return -EFAULT; 303 } 304 305 pll = val / 12; 306 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ 307 /* Revisit this for higher speed CPUs */ 308 spin_unlock_irqrestore(&pm_lock, flags); 309 return -EFAULT; 310 } 311 312 old_baud_base = get_au1x00_uart_baud_base(); 313 old_cpu_freq = get_au1x00_speed(); 314 315 new_cpu_freq = pll * 12 * 1000000; 316 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL) 317 & 0x03) + 2) * 16)); 318 set_au1x00_speed(new_cpu_freq); 319 set_au1x00_uart_baud_base(new_baud_base); 320 321 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; 322 new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) | 323 (au_readl(MEM_SDREFCFG) & ~0x1ffffff); 324 325 au_writel(pll, SYS_CPUPLL); 326 au_sync_delay(1); 327 au_writel(new_refresh, MEM_SDREFCFG); 328 au_sync_delay(1); 329 330 for (i = 0; i < 4; i++) 331 if (au_readl(UART_BASE + UART_MOD_CNTRL + 332 i * 0x00100000) == 3) { 333 old_clk = au_readl(UART_BASE + UART_CLK + 334 i * 0x00100000); 335 baud_rate = old_baud_base / old_clk; 336 /* 337 * We won't get an exact baud rate and the error 338 * could be significant enough that our new 339 * calculation will result in a clock that will 340 * give us a baud rate that's too far off from 341 * what we really want. 342 */ 343 if (baud_rate > 100000) 344 baud_rate = 115200; 345 else if (baud_rate > 50000) 346 baud_rate = 57600; 347 else if (baud_rate > 30000) 348 baud_rate = 38400; 349 else if (baud_rate > 17000) 350 baud_rate = 19200; 351 else 352 baud_rate = 9600; 353 new_clk = new_baud_base / baud_rate; 354 au_writel(new_clk, UART_BASE + UART_CLK + 355 i * 0x00100000); 356 au_sync_delay(10); 357 } 358 } 359 360 /* 361 * We don't want _any_ interrupts other than match20. Otherwise our 362 * au1000_calibrate_delay() calculation will be off, potentially a lot. 363 */ 364 intc0_mask = save_local_and_disable(0); 365 intc1_mask = save_local_and_disable(1); 366 val = 1 << (AU1000_TOY_MATCH2_INT - AU1000_INTC0_INT_BASE); 367 au_writel(val, IC0_MASKSET); /* unmask */ 368 au_writel(val, IC0_WAKESET); /* enable wake-from-sleep */ 369 au_sync(); 370 spin_unlock_irqrestore(&pm_lock, flags); 371 au1000_calibrate_delay(); 372 restore_local_and_enable(0, intc0_mask); 373 restore_local_and_enable(1, intc1_mask); 374 375 return retval; 376 } 377 378 379 static struct ctl_table pm_table[] = { 380 { 381 .ctl_name = CTL_UNNUMBERED, 382 .procname = "sleep", 383 .data = NULL, 384 .maxlen = 0, 385 .mode = 0600, 386 .proc_handler = &pm_do_sleep 387 }, 388 { 389 .ctl_name = CTL_UNNUMBERED, 390 .procname = "freq", 391 .data = NULL, 392 .maxlen = 0, 393 .mode = 0600, 394 .proc_handler = &pm_do_freq 395 }, 396 {} 397 }; 398 399 static struct ctl_table pm_dir_table[] = { 400 { 401 .ctl_name = CTL_UNNUMBERED, 402 .procname = "pm", 403 .mode = 0555, 404 .child = pm_table 405 }, 406 {} 407 }; 408 409 /* 410 * Initialize power interface 411 */ 412 static int __init pm_init(void) 413 { 414 register_sysctl_table(pm_dir_table); 415 return 0; 416 } 417 418 __initcall(pm_init); 419 420 /* 421 * This is right out of init/main.c 422 */ 423 424 /* 425 * This is the number of bits of precision for the loops_per_jiffy. 426 * Each bit takes on average 1.5/HZ seconds. This (like the original) 427 * is a little better than 1%. 428 */ 429 #define LPS_PREC 8 430 431 static void au1000_calibrate_delay(void) 432 { 433 unsigned long ticks, loopbit; 434 int lps_precision = LPS_PREC; 435 436 loops_per_jiffy = 1 << 12; 437 438 while (loops_per_jiffy <<= 1) { 439 /* Wait for "start of" clock tick */ 440 ticks = jiffies; 441 while (ticks == jiffies) 442 /* nothing */ ; 443 /* Go ... */ 444 ticks = jiffies; 445 __delay(loops_per_jiffy); 446 ticks = jiffies - ticks; 447 if (ticks) 448 break; 449 } 450 451 /* 452 * Do a binary approximation to get loops_per_jiffy set to be equal 453 * one clock (up to lps_precision bits) 454 */ 455 loops_per_jiffy >>= 1; 456 loopbit = loops_per_jiffy; 457 while (lps_precision-- && (loopbit >>= 1)) { 458 loops_per_jiffy |= loopbit; 459 ticks = jiffies; 460 while (ticks == jiffies); 461 ticks = jiffies; 462 __delay(loops_per_jiffy); 463 if (jiffies != ticks) /* longer than 1 tick */ 464 loops_per_jiffy &= ~loopbit; 465 } 466 } 467 #endif /* CONFIG_PM */ 468