1 /* 2 * Platform device support for Au1x00 SoCs. 3 * 4 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> 5 * 6 * (C) Copyright Embedded Alley Solutions, Inc 2005 7 * Author: Pantelis Antoniou <pantelis@embeddedalley.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/etherdevice.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/serial_8250.h> 20 #include <linux/slab.h> 21 #include <linux/usb/ehci_pdriver.h> 22 #include <linux/usb/ohci_pdriver.h> 23 24 #include <asm/mach-au1x00/au1000.h> 25 #include <asm/mach-au1x00/au1xxx_dbdma.h> 26 #include <asm/mach-au1x00/au1100_mmc.h> 27 #include <asm/mach-au1x00/au1xxx_eth.h> 28 29 #include <prom.h> 30 31 static void alchemy_8250_pm(struct uart_port *port, unsigned int state, 32 unsigned int old_state) 33 { 34 #ifdef CONFIG_SERIAL_8250 35 switch (state) { 36 case 0: 37 alchemy_uart_enable(CPHYSADDR(port->membase)); 38 serial8250_do_pm(port, state, old_state); 39 break; 40 case 3: /* power off */ 41 serial8250_do_pm(port, state, old_state); 42 alchemy_uart_disable(CPHYSADDR(port->membase)); 43 break; 44 default: 45 serial8250_do_pm(port, state, old_state); 46 break; 47 } 48 #endif 49 } 50 51 #define PORT(_base, _irq) \ 52 { \ 53 .mapbase = _base, \ 54 .irq = _irq, \ 55 .regshift = 2, \ 56 .iotype = UPIO_AU, \ 57 .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ 58 UPF_FIXED_TYPE, \ 59 .type = PORT_16550A, \ 60 .pm = alchemy_8250_pm, \ 61 } 62 63 static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = { 64 [ALCHEMY_CPU_AU1000] = { 65 PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT), 66 PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT), 67 PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT), 68 PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT), 69 }, 70 [ALCHEMY_CPU_AU1500] = { 71 PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT), 72 PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT), 73 }, 74 [ALCHEMY_CPU_AU1100] = { 75 PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT), 76 PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT), 77 PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT), 78 }, 79 [ALCHEMY_CPU_AU1550] = { 80 PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT), 81 PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT), 82 PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT), 83 }, 84 [ALCHEMY_CPU_AU1200] = { 85 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), 86 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), 87 }, 88 [ALCHEMY_CPU_AU1300] = { 89 PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT), 90 PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT), 91 PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT), 92 PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT), 93 }, 94 }; 95 96 static struct platform_device au1xx0_uart_device = { 97 .name = "serial8250", 98 .id = PLAT8250_DEV_AU1X00, 99 }; 100 101 static void __init alchemy_setup_uarts(int ctype) 102 { 103 long uartclk; 104 int s = sizeof(struct plat_serial8250_port); 105 int c = alchemy_get_uarts(ctype); 106 struct plat_serial8250_port *ports; 107 struct clk *clk = clk_get(NULL, ALCHEMY_PERIPH_CLK); 108 109 if (IS_ERR(clk)) 110 return; 111 if (clk_prepare_enable(clk)) { 112 clk_put(clk); 113 return; 114 } 115 uartclk = clk_get_rate(clk); 116 clk_put(clk); 117 118 ports = kcalloc(s, (c + 1), GFP_KERNEL); 119 if (!ports) { 120 printk(KERN_INFO "Alchemy: no memory for UART data\n"); 121 return; 122 } 123 memcpy(ports, au1x00_uart_data[ctype], s * c); 124 au1xx0_uart_device.dev.platform_data = ports; 125 126 /* Fill up uartclk. */ 127 for (s = 0; s < c; s++) 128 ports[s].uartclk = uartclk; 129 if (platform_device_register(&au1xx0_uart_device)) 130 printk(KERN_INFO "Alchemy: failed to register UARTs\n"); 131 } 132 133 134 static u64 alchemy_all_dmamask = DMA_BIT_MASK(32); 135 136 /* Power on callback for the ehci platform driver */ 137 static int alchemy_ehci_power_on(struct platform_device *pdev) 138 { 139 return alchemy_usb_control(ALCHEMY_USB_EHCI0, 1); 140 } 141 142 /* Power off/suspend callback for the ehci platform driver */ 143 static void alchemy_ehci_power_off(struct platform_device *pdev) 144 { 145 alchemy_usb_control(ALCHEMY_USB_EHCI0, 0); 146 } 147 148 static struct usb_ehci_pdata alchemy_ehci_pdata = { 149 .no_io_watchdog = 1, 150 .power_on = alchemy_ehci_power_on, 151 .power_off = alchemy_ehci_power_off, 152 .power_suspend = alchemy_ehci_power_off, 153 }; 154 155 /* Power on callback for the ohci platform driver */ 156 static int alchemy_ohci_power_on(struct platform_device *pdev) 157 { 158 int unit; 159 160 unit = (pdev->id == 1) ? 161 ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0; 162 163 return alchemy_usb_control(unit, 1); 164 } 165 166 /* Power off/suspend callback for the ohci platform driver */ 167 static void alchemy_ohci_power_off(struct platform_device *pdev) 168 { 169 int unit; 170 171 unit = (pdev->id == 1) ? 172 ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0; 173 174 alchemy_usb_control(unit, 0); 175 } 176 177 static struct usb_ohci_pdata alchemy_ohci_pdata = { 178 .power_on = alchemy_ohci_power_on, 179 .power_off = alchemy_ohci_power_off, 180 .power_suspend = alchemy_ohci_power_off, 181 }; 182 183 static unsigned long alchemy_ohci_data[][2] __initdata = { 184 [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT }, 185 [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT }, 186 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, 187 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, 188 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, 189 [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT }, 190 }; 191 192 static unsigned long alchemy_ehci_data[][2] __initdata = { 193 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, 194 [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT }, 195 }; 196 197 static int __init _new_usbres(struct resource **r, struct platform_device **d) 198 { 199 *r = kcalloc(2, sizeof(struct resource), GFP_KERNEL); 200 if (!*r) 201 return -ENOMEM; 202 *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL); 203 if (!*d) { 204 kfree(*r); 205 return -ENOMEM; 206 } 207 208 (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32); 209 (*d)->num_resources = 2; 210 (*d)->resource = *r; 211 212 return 0; 213 } 214 215 static void __init alchemy_setup_usb(int ctype) 216 { 217 struct resource *res; 218 struct platform_device *pdev; 219 220 /* setup OHCI0. Every variant has one */ 221 if (_new_usbres(&res, &pdev)) 222 return; 223 224 res[0].start = alchemy_ohci_data[ctype][0]; 225 res[0].end = res[0].start + 0x100 - 1; 226 res[0].flags = IORESOURCE_MEM; 227 res[1].start = alchemy_ohci_data[ctype][1]; 228 res[1].end = res[1].start; 229 res[1].flags = IORESOURCE_IRQ; 230 pdev->name = "ohci-platform"; 231 pdev->id = 0; 232 pdev->dev.dma_mask = &alchemy_all_dmamask; 233 pdev->dev.platform_data = &alchemy_ohci_pdata; 234 235 if (platform_device_register(pdev)) 236 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); 237 238 239 /* setup EHCI0: Au1200/Au1300 */ 240 if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) { 241 if (_new_usbres(&res, &pdev)) 242 return; 243 244 res[0].start = alchemy_ehci_data[ctype][0]; 245 res[0].end = res[0].start + 0x100 - 1; 246 res[0].flags = IORESOURCE_MEM; 247 res[1].start = alchemy_ehci_data[ctype][1]; 248 res[1].end = res[1].start; 249 res[1].flags = IORESOURCE_IRQ; 250 pdev->name = "ehci-platform"; 251 pdev->id = 0; 252 pdev->dev.dma_mask = &alchemy_all_dmamask; 253 pdev->dev.platform_data = &alchemy_ehci_pdata; 254 255 if (platform_device_register(pdev)) 256 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); 257 } 258 259 /* Au1300: OHCI1 */ 260 if (ctype == ALCHEMY_CPU_AU1300) { 261 if (_new_usbres(&res, &pdev)) 262 return; 263 264 res[0].start = AU1300_USB_OHCI1_PHYS_ADDR; 265 res[0].end = res[0].start + 0x100 - 1; 266 res[0].flags = IORESOURCE_MEM; 267 res[1].start = AU1300_USB_INT; 268 res[1].end = res[1].start; 269 res[1].flags = IORESOURCE_IRQ; 270 pdev->name = "ohci-platform"; 271 pdev->id = 1; 272 pdev->dev.dma_mask = &alchemy_all_dmamask; 273 pdev->dev.platform_data = &alchemy_ohci_pdata; 274 275 if (platform_device_register(pdev)) 276 printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n"); 277 } 278 } 279 280 /* Macro to help defining the Ethernet MAC resources */ 281 #define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */ 282 #define MAC_RES(_base, _enable, _irq, _macdma) \ 283 { \ 284 .start = _base, \ 285 .end = _base + 0xffff, \ 286 .flags = IORESOURCE_MEM, \ 287 }, \ 288 { \ 289 .start = _enable, \ 290 .end = _enable + 0x3, \ 291 .flags = IORESOURCE_MEM, \ 292 }, \ 293 { \ 294 .start = _irq, \ 295 .end = _irq, \ 296 .flags = IORESOURCE_IRQ \ 297 }, \ 298 { \ 299 .start = _macdma, \ 300 .end = _macdma + 0x1ff, \ 301 .flags = IORESOURCE_MEM, \ 302 } 303 304 static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = { 305 [ALCHEMY_CPU_AU1000] = { 306 MAC_RES(AU1000_MAC0_PHYS_ADDR, 307 AU1000_MACEN_PHYS_ADDR, 308 AU1000_MAC0_DMA_INT, 309 AU1000_MACDMA0_PHYS_ADDR) 310 }, 311 [ALCHEMY_CPU_AU1500] = { 312 MAC_RES(AU1500_MAC0_PHYS_ADDR, 313 AU1500_MACEN_PHYS_ADDR, 314 AU1500_MAC0_DMA_INT, 315 AU1000_MACDMA0_PHYS_ADDR) 316 }, 317 [ALCHEMY_CPU_AU1100] = { 318 MAC_RES(AU1000_MAC0_PHYS_ADDR, 319 AU1000_MACEN_PHYS_ADDR, 320 AU1100_MAC0_DMA_INT, 321 AU1000_MACDMA0_PHYS_ADDR) 322 }, 323 [ALCHEMY_CPU_AU1550] = { 324 MAC_RES(AU1000_MAC0_PHYS_ADDR, 325 AU1000_MACEN_PHYS_ADDR, 326 AU1550_MAC0_DMA_INT, 327 AU1000_MACDMA0_PHYS_ADDR) 328 }, 329 }; 330 331 static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { 332 .phy1_search_mac0 = 1, 333 }; 334 335 static struct platform_device au1xxx_eth0_device = { 336 .name = "au1000-eth", 337 .id = 0, 338 .num_resources = MAC_RES_COUNT, 339 .dev = { 340 .dma_mask = &alchemy_all_dmamask, 341 .coherent_dma_mask = DMA_BIT_MASK(32), 342 .platform_data = &au1xxx_eth0_platform_data, 343 }, 344 }; 345 346 static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = { 347 [ALCHEMY_CPU_AU1000] = { 348 MAC_RES(AU1000_MAC1_PHYS_ADDR, 349 AU1000_MACEN_PHYS_ADDR + 4, 350 AU1000_MAC1_DMA_INT, 351 AU1000_MACDMA1_PHYS_ADDR) 352 }, 353 [ALCHEMY_CPU_AU1500] = { 354 MAC_RES(AU1500_MAC1_PHYS_ADDR, 355 AU1500_MACEN_PHYS_ADDR + 4, 356 AU1500_MAC1_DMA_INT, 357 AU1000_MACDMA1_PHYS_ADDR) 358 }, 359 [ALCHEMY_CPU_AU1550] = { 360 MAC_RES(AU1000_MAC1_PHYS_ADDR, 361 AU1000_MACEN_PHYS_ADDR + 4, 362 AU1550_MAC1_DMA_INT, 363 AU1000_MACDMA1_PHYS_ADDR) 364 }, 365 }; 366 367 static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { 368 .phy1_search_mac0 = 1, 369 }; 370 371 static struct platform_device au1xxx_eth1_device = { 372 .name = "au1000-eth", 373 .id = 1, 374 .num_resources = MAC_RES_COUNT, 375 .dev = { 376 .dma_mask = &alchemy_all_dmamask, 377 .coherent_dma_mask = DMA_BIT_MASK(32), 378 .platform_data = &au1xxx_eth1_platform_data, 379 }, 380 }; 381 382 void __init au1xxx_override_eth_cfg(unsigned int port, 383 struct au1000_eth_platform_data *eth_data) 384 { 385 if (!eth_data || port > 1) 386 return; 387 388 if (port == 0) 389 memcpy(&au1xxx_eth0_platform_data, eth_data, 390 sizeof(struct au1000_eth_platform_data)); 391 else 392 memcpy(&au1xxx_eth1_platform_data, eth_data, 393 sizeof(struct au1000_eth_platform_data)); 394 } 395 396 static void __init alchemy_setup_macs(int ctype) 397 { 398 int ret, i; 399 unsigned char ethaddr[6]; 400 struct resource *macres; 401 402 /* Handle 1st MAC */ 403 if (alchemy_get_macs(ctype) < 1) 404 return; 405 406 macres = kmemdup(au1xxx_eth0_resources[ctype], 407 sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); 408 if (!macres) { 409 printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n"); 410 return; 411 } 412 au1xxx_eth0_device.resource = macres; 413 414 i = prom_get_ethernet_addr(ethaddr); 415 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac)) 416 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6); 417 418 ret = platform_device_register(&au1xxx_eth0_device); 419 if (ret) 420 printk(KERN_INFO "Alchemy: failed to register MAC0\n"); 421 422 423 /* Handle 2nd MAC */ 424 if (alchemy_get_macs(ctype) < 2) 425 return; 426 427 macres = kmemdup(au1xxx_eth1_resources[ctype], 428 sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); 429 if (!macres) { 430 printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n"); 431 return; 432 } 433 au1xxx_eth1_device.resource = macres; 434 435 ethaddr[5] += 1; /* next addr for 2nd MAC */ 436 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac)) 437 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6); 438 439 /* Register second MAC if enabled in pinfunc */ 440 if (!(alchemy_rdsys(AU1000_SYS_PINFUNC) & SYS_PF_NI2)) { 441 ret = platform_device_register(&au1xxx_eth1_device); 442 if (ret) 443 printk(KERN_INFO "Alchemy: failed to register MAC1\n"); 444 } 445 } 446 447 static int __init au1xxx_platform_init(void) 448 { 449 int ctype = alchemy_get_cputype(); 450 451 alchemy_setup_uarts(ctype); 452 alchemy_setup_macs(ctype); 453 alchemy_setup_usb(ctype); 454 455 return 0; 456 } 457 458 arch_initcall(au1xxx_platform_init); 459