1 /* 2 * Platform device support for Au1x00 SoCs. 3 * 4 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> 5 * 6 * (C) Copyright Embedded Alley Solutions, Inc 2005 7 * Author: Pantelis Antoniou <pantelis@embeddedalley.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/dma-mapping.h> 15 #include <linux/etherdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/serial_8250.h> 18 #include <linux/init.h> 19 20 #include <asm/mach-au1x00/au1xxx.h> 21 #include <asm/mach-au1x00/au1xxx_dbdma.h> 22 #include <asm/mach-au1x00/au1100_mmc.h> 23 #include <asm/mach-au1x00/au1xxx_eth.h> 24 25 #include <prom.h> 26 27 static void alchemy_8250_pm(struct uart_port *port, unsigned int state, 28 unsigned int old_state) 29 { 30 switch (state) { 31 case 0: 32 if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) { 33 /* power-on sequence as suggested in the databooks */ 34 __raw_writel(0, port->membase + UART_MOD_CNTRL); 35 wmb(); 36 __raw_writel(1, port->membase + UART_MOD_CNTRL); 37 wmb(); 38 } 39 __raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */ 40 wmb(); 41 serial8250_do_pm(port, state, old_state); 42 break; 43 case 3: /* power off */ 44 serial8250_do_pm(port, state, old_state); 45 __raw_writel(0, port->membase + UART_MOD_CNTRL); 46 wmb(); 47 break; 48 default: 49 serial8250_do_pm(port, state, old_state); 50 break; 51 } 52 } 53 54 #define PORT(_base, _irq) \ 55 { \ 56 .mapbase = _base, \ 57 .irq = _irq, \ 58 .regshift = 2, \ 59 .iotype = UPIO_AU, \ 60 .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ 61 UPF_FIXED_TYPE, \ 62 .type = PORT_16550A, \ 63 .pm = alchemy_8250_pm, \ 64 } 65 66 static struct plat_serial8250_port au1x00_uart_data[] = { 67 #if defined(CONFIG_SOC_AU1000) 68 PORT(UART0_PHYS_ADDR, AU1000_UART0_INT), 69 PORT(UART1_PHYS_ADDR, AU1000_UART1_INT), 70 PORT(UART2_PHYS_ADDR, AU1000_UART2_INT), 71 PORT(UART3_PHYS_ADDR, AU1000_UART3_INT), 72 #elif defined(CONFIG_SOC_AU1500) 73 PORT(UART0_PHYS_ADDR, AU1500_UART0_INT), 74 PORT(UART3_PHYS_ADDR, AU1500_UART3_INT), 75 #elif defined(CONFIG_SOC_AU1100) 76 PORT(UART0_PHYS_ADDR, AU1100_UART0_INT), 77 PORT(UART1_PHYS_ADDR, AU1100_UART1_INT), 78 PORT(UART3_PHYS_ADDR, AU1100_UART3_INT), 79 #elif defined(CONFIG_SOC_AU1550) 80 PORT(UART0_PHYS_ADDR, AU1550_UART0_INT), 81 PORT(UART1_PHYS_ADDR, AU1550_UART1_INT), 82 PORT(UART3_PHYS_ADDR, AU1550_UART3_INT), 83 #elif defined(CONFIG_SOC_AU1200) 84 PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), 85 PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), 86 #endif 87 { }, 88 }; 89 90 static struct platform_device au1xx0_uart_device = { 91 .name = "serial8250", 92 .id = PLAT8250_DEV_AU1X00, 93 .dev = { 94 .platform_data = au1x00_uart_data, 95 }, 96 }; 97 98 /* OHCI (USB full speed host controller) */ 99 static struct resource au1xxx_usb_ohci_resources[] = { 100 [0] = { 101 .start = USB_OHCI_BASE, 102 .end = USB_OHCI_BASE + USB_OHCI_LEN - 1, 103 .flags = IORESOURCE_MEM, 104 }, 105 [1] = { 106 .start = FOR_PLATFORM_C_USB_HOST_INT, 107 .end = FOR_PLATFORM_C_USB_HOST_INT, 108 .flags = IORESOURCE_IRQ, 109 }, 110 }; 111 112 /* The dmamask must be set for OHCI to work */ 113 static u64 ohci_dmamask = DMA_BIT_MASK(32); 114 115 static struct platform_device au1xxx_usb_ohci_device = { 116 .name = "au1xxx-ohci", 117 .id = 0, 118 .dev = { 119 .dma_mask = &ohci_dmamask, 120 .coherent_dma_mask = DMA_BIT_MASK(32), 121 }, 122 .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), 123 .resource = au1xxx_usb_ohci_resources, 124 }; 125 126 /*** AU1100 LCD controller ***/ 127 128 #ifdef CONFIG_FB_AU1100 129 static struct resource au1100_lcd_resources[] = { 130 [0] = { 131 .start = LCD_PHYS_ADDR, 132 .end = LCD_PHYS_ADDR + 0x800 - 1, 133 .flags = IORESOURCE_MEM, 134 }, 135 [1] = { 136 .start = AU1100_LCD_INT, 137 .end = AU1100_LCD_INT, 138 .flags = IORESOURCE_IRQ, 139 } 140 }; 141 142 static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); 143 144 static struct platform_device au1100_lcd_device = { 145 .name = "au1100-lcd", 146 .id = 0, 147 .dev = { 148 .dma_mask = &au1100_lcd_dmamask, 149 .coherent_dma_mask = DMA_BIT_MASK(32), 150 }, 151 .num_resources = ARRAY_SIZE(au1100_lcd_resources), 152 .resource = au1100_lcd_resources, 153 }; 154 #endif 155 156 #ifdef CONFIG_SOC_AU1200 157 /* EHCI (USB high speed host controller) */ 158 static struct resource au1xxx_usb_ehci_resources[] = { 159 [0] = { 160 .start = USB_EHCI_BASE, 161 .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, 162 .flags = IORESOURCE_MEM, 163 }, 164 [1] = { 165 .start = AU1200_USB_INT, 166 .end = AU1200_USB_INT, 167 .flags = IORESOURCE_IRQ, 168 }, 169 }; 170 171 static u64 ehci_dmamask = DMA_BIT_MASK(32); 172 173 static struct platform_device au1xxx_usb_ehci_device = { 174 .name = "au1xxx-ehci", 175 .id = 0, 176 .dev = { 177 .dma_mask = &ehci_dmamask, 178 .coherent_dma_mask = DMA_BIT_MASK(32), 179 }, 180 .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources), 181 .resource = au1xxx_usb_ehci_resources, 182 }; 183 184 /* Au1200 UDC (USB gadget controller) */ 185 static struct resource au1xxx_usb_gdt_resources[] = { 186 [0] = { 187 .start = USB_UDC_BASE, 188 .end = USB_UDC_BASE + USB_UDC_LEN - 1, 189 .flags = IORESOURCE_MEM, 190 }, 191 [1] = { 192 .start = AU1200_USB_INT, 193 .end = AU1200_USB_INT, 194 .flags = IORESOURCE_IRQ, 195 }, 196 }; 197 198 static u64 udc_dmamask = DMA_BIT_MASK(32); 199 200 static struct platform_device au1xxx_usb_gdt_device = { 201 .name = "au1xxx-udc", 202 .id = 0, 203 .dev = { 204 .dma_mask = &udc_dmamask, 205 .coherent_dma_mask = DMA_BIT_MASK(32), 206 }, 207 .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources), 208 .resource = au1xxx_usb_gdt_resources, 209 }; 210 211 /* Au1200 UOC (USB OTG controller) */ 212 static struct resource au1xxx_usb_otg_resources[] = { 213 [0] = { 214 .start = USB_UOC_BASE, 215 .end = USB_UOC_BASE + USB_UOC_LEN - 1, 216 .flags = IORESOURCE_MEM, 217 }, 218 [1] = { 219 .start = AU1200_USB_INT, 220 .end = AU1200_USB_INT, 221 .flags = IORESOURCE_IRQ, 222 }, 223 }; 224 225 static u64 uoc_dmamask = DMA_BIT_MASK(32); 226 227 static struct platform_device au1xxx_usb_otg_device = { 228 .name = "au1xxx-uoc", 229 .id = 0, 230 .dev = { 231 .dma_mask = &uoc_dmamask, 232 .coherent_dma_mask = DMA_BIT_MASK(32), 233 }, 234 .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources), 235 .resource = au1xxx_usb_otg_resources, 236 }; 237 238 static struct resource au1200_lcd_resources[] = { 239 [0] = { 240 .start = LCD_PHYS_ADDR, 241 .end = LCD_PHYS_ADDR + 0x800 - 1, 242 .flags = IORESOURCE_MEM, 243 }, 244 [1] = { 245 .start = AU1200_LCD_INT, 246 .end = AU1200_LCD_INT, 247 .flags = IORESOURCE_IRQ, 248 } 249 }; 250 251 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); 252 253 static struct platform_device au1200_lcd_device = { 254 .name = "au1200-lcd", 255 .id = 0, 256 .dev = { 257 .dma_mask = &au1200_lcd_dmamask, 258 .coherent_dma_mask = DMA_BIT_MASK(32), 259 }, 260 .num_resources = ARRAY_SIZE(au1200_lcd_resources), 261 .resource = au1200_lcd_resources, 262 }; 263 264 static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 265 266 extern struct au1xmmc_platform_data au1xmmc_platdata[2]; 267 268 static struct resource au1200_mmc0_resources[] = { 269 [0] = { 270 .start = SD0_PHYS_ADDR, 271 .end = SD0_PHYS_ADDR + 0x7ffff, 272 .flags = IORESOURCE_MEM, 273 }, 274 [1] = { 275 .start = AU1200_SD_INT, 276 .end = AU1200_SD_INT, 277 .flags = IORESOURCE_IRQ, 278 }, 279 [2] = { 280 .start = DSCR_CMD0_SDMS_TX0, 281 .end = DSCR_CMD0_SDMS_TX0, 282 .flags = IORESOURCE_DMA, 283 }, 284 [3] = { 285 .start = DSCR_CMD0_SDMS_RX0, 286 .end = DSCR_CMD0_SDMS_RX0, 287 .flags = IORESOURCE_DMA, 288 } 289 }; 290 291 static struct platform_device au1200_mmc0_device = { 292 .name = "au1xxx-mmc", 293 .id = 0, 294 .dev = { 295 .dma_mask = &au1xxx_mmc_dmamask, 296 .coherent_dma_mask = DMA_BIT_MASK(32), 297 .platform_data = &au1xmmc_platdata[0], 298 }, 299 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 300 .resource = au1200_mmc0_resources, 301 }; 302 303 #ifndef CONFIG_MIPS_DB1200 304 static struct resource au1200_mmc1_resources[] = { 305 [0] = { 306 .start = SD1_PHYS_ADDR, 307 .end = SD1_PHYS_ADDR + 0x7ffff, 308 .flags = IORESOURCE_MEM, 309 }, 310 [1] = { 311 .start = AU1200_SD_INT, 312 .end = AU1200_SD_INT, 313 .flags = IORESOURCE_IRQ, 314 }, 315 [2] = { 316 .start = DSCR_CMD0_SDMS_TX1, 317 .end = DSCR_CMD0_SDMS_TX1, 318 .flags = IORESOURCE_DMA, 319 }, 320 [3] = { 321 .start = DSCR_CMD0_SDMS_RX1, 322 .end = DSCR_CMD0_SDMS_RX1, 323 .flags = IORESOURCE_DMA, 324 } 325 }; 326 327 static struct platform_device au1200_mmc1_device = { 328 .name = "au1xxx-mmc", 329 .id = 1, 330 .dev = { 331 .dma_mask = &au1xxx_mmc_dmamask, 332 .coherent_dma_mask = DMA_BIT_MASK(32), 333 .platform_data = &au1xmmc_platdata[1], 334 }, 335 .num_resources = ARRAY_SIZE(au1200_mmc1_resources), 336 .resource = au1200_mmc1_resources, 337 }; 338 #endif /* #ifndef CONFIG_MIPS_DB1200 */ 339 #endif /* #ifdef CONFIG_SOC_AU1200 */ 340 341 /* All Alchemy demoboards with I2C have this #define in their headers */ 342 #ifdef SMBUS_PSC_BASE 343 static struct resource pbdb_smbus_resources[] = { 344 { 345 .start = CPHYSADDR(SMBUS_PSC_BASE), 346 .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff), 347 .flags = IORESOURCE_MEM, 348 }, 349 }; 350 351 static struct platform_device pbdb_smbus_device = { 352 .name = "au1xpsc_smbus", 353 .id = 0, /* bus number */ 354 .num_resources = ARRAY_SIZE(pbdb_smbus_resources), 355 .resource = pbdb_smbus_resources, 356 }; 357 #endif 358 359 /* Macro to help defining the Ethernet MAC resources */ 360 #define MAC_RES(_base, _enable, _irq) \ 361 { \ 362 .start = CPHYSADDR(_base), \ 363 .end = CPHYSADDR(_base + 0xffff), \ 364 .flags = IORESOURCE_MEM, \ 365 }, \ 366 { \ 367 .start = CPHYSADDR(_enable), \ 368 .end = CPHYSADDR(_enable + 0x3), \ 369 .flags = IORESOURCE_MEM, \ 370 }, \ 371 { \ 372 .start = _irq, \ 373 .end = _irq, \ 374 .flags = IORESOURCE_IRQ \ 375 } 376 377 static struct resource au1xxx_eth0_resources[] = { 378 #if defined(CONFIG_SOC_AU1000) 379 MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), 380 #elif defined(CONFIG_SOC_AU1100) 381 MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), 382 #elif defined(CONFIG_SOC_AU1550) 383 MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), 384 #elif defined(CONFIG_SOC_AU1500) 385 MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), 386 #endif 387 }; 388 389 390 static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { 391 .phy1_search_mac0 = 1, 392 }; 393 394 static struct platform_device au1xxx_eth0_device = { 395 .name = "au1000-eth", 396 .id = 0, 397 .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), 398 .resource = au1xxx_eth0_resources, 399 .dev.platform_data = &au1xxx_eth0_platform_data, 400 }; 401 402 #ifndef CONFIG_SOC_AU1100 403 static struct resource au1xxx_eth1_resources[] = { 404 #if defined(CONFIG_SOC_AU1000) 405 MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), 406 #elif defined(CONFIG_SOC_AU1550) 407 MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), 408 #elif defined(CONFIG_SOC_AU1500) 409 MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), 410 #endif 411 }; 412 413 static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { 414 .phy1_search_mac0 = 1, 415 }; 416 417 static struct platform_device au1xxx_eth1_device = { 418 .name = "au1000-eth", 419 .id = 1, 420 .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), 421 .resource = au1xxx_eth1_resources, 422 .dev.platform_data = &au1xxx_eth1_platform_data, 423 }; 424 #endif 425 426 void __init au1xxx_override_eth_cfg(unsigned int port, 427 struct au1000_eth_platform_data *eth_data) 428 { 429 if (!eth_data || port > 1) 430 return; 431 432 if (port == 0) 433 memcpy(&au1xxx_eth0_platform_data, eth_data, 434 sizeof(struct au1000_eth_platform_data)); 435 #ifndef CONFIG_SOC_AU1100 436 else 437 memcpy(&au1xxx_eth1_platform_data, eth_data, 438 sizeof(struct au1000_eth_platform_data)); 439 #endif 440 } 441 442 static struct platform_device *au1xxx_platform_devices[] __initdata = { 443 &au1xx0_uart_device, 444 &au1xxx_usb_ohci_device, 445 #ifdef CONFIG_FB_AU1100 446 &au1100_lcd_device, 447 #endif 448 #ifdef CONFIG_SOC_AU1200 449 &au1xxx_usb_ehci_device, 450 &au1xxx_usb_gdt_device, 451 &au1xxx_usb_otg_device, 452 &au1200_lcd_device, 453 &au1200_mmc0_device, 454 #ifndef CONFIG_MIPS_DB1200 455 &au1200_mmc1_device, 456 #endif 457 #endif 458 #ifdef SMBUS_PSC_BASE 459 &pbdb_smbus_device, 460 #endif 461 &au1xxx_eth0_device, 462 }; 463 464 static int __init au1xxx_platform_init(void) 465 { 466 unsigned int uartclk = get_au1x00_uart_baud_base() * 16; 467 int err, i; 468 unsigned char ethaddr[6]; 469 470 /* Fill up uartclk. */ 471 for (i = 0; au1x00_uart_data[i].flags; i++) 472 au1x00_uart_data[i].uartclk = uartclk; 473 474 /* use firmware-provided mac addr if available and necessary */ 475 i = prom_get_ethernet_addr(ethaddr); 476 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac)) 477 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6); 478 479 err = platform_add_devices(au1xxx_platform_devices, 480 ARRAY_SIZE(au1xxx_platform_devices)); 481 #ifndef CONFIG_SOC_AU1100 482 ethaddr[5] += 1; /* next addr for 2nd MAC */ 483 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac)) 484 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6); 485 486 /* Register second MAC if enabled in pinfunc */ 487 if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) 488 err = platform_device_register(&au1xxx_eth1_device); 489 #endif 490 491 return err; 492 } 493 494 arch_initcall(au1xxx_platform_init); 495