1 /* 2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org> 3 * GPIOLIB support for Alchemy chips. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, write to the Free Software Foundation, Inc., 23 * 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * Notes : 26 * This file must ONLY be built when CONFIG_GPIOLIB=y and 27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! 28 * au1000 SoC have only one GPIO block : GPIO1 29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 30 */ 31 32 #include <linux/init.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/types.h> 36 #include <linux/gpio.h> 37 #include <asm/mach-au1x00/gpio-au1000.h> 38 39 static int gpio2_get(struct gpio_chip *chip, unsigned offset) 40 { 41 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); 42 } 43 44 static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value) 45 { 46 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); 47 } 48 49 static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset) 50 { 51 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); 52 } 53 54 static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset, 55 int value) 56 { 57 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, 58 value); 59 } 60 61 static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) 62 { 63 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); 64 } 65 66 67 static int gpio1_get(struct gpio_chip *chip, unsigned offset) 68 { 69 return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE); 70 } 71 72 static void gpio1_set(struct gpio_chip *chip, 73 unsigned offset, int value) 74 { 75 alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value); 76 } 77 78 static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset) 79 { 80 return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE); 81 } 82 83 static int gpio1_direction_output(struct gpio_chip *chip, 84 unsigned offset, int value) 85 { 86 return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE, 87 value); 88 } 89 90 static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset) 91 { 92 return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE); 93 } 94 95 struct gpio_chip alchemy_gpio_chip[] = { 96 [0] = { 97 .label = "alchemy-gpio1", 98 .direction_input = gpio1_direction_input, 99 .direction_output = gpio1_direction_output, 100 .get = gpio1_get, 101 .set = gpio1_set, 102 .to_irq = gpio1_to_irq, 103 .base = ALCHEMY_GPIO1_BASE, 104 .ngpio = ALCHEMY_GPIO1_NUM, 105 }, 106 [1] = { 107 .label = "alchemy-gpio2", 108 .direction_input = gpio2_direction_input, 109 .direction_output = gpio2_direction_output, 110 .get = gpio2_get, 111 .set = gpio2_set, 112 .to_irq = gpio2_to_irq, 113 .base = ALCHEMY_GPIO2_BASE, 114 .ngpio = ALCHEMY_GPIO2_NUM, 115 }, 116 }; 117 118 static int __init alchemy_gpiochip_init(void) 119 { 120 int ret = 0; 121 122 switch (alchemy_get_cputype()) { 123 case ALCHEMY_CPU_AU1000: 124 ret = gpiochip_add(&alchemy_gpio_chip[0]); 125 break; 126 case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200: 127 ret = gpiochip_add(&alchemy_gpio_chip[0]); 128 ret |= gpiochip_add(&alchemy_gpio_chip[1]); 129 break; 130 } 131 return ret; 132 } 133 arch_initcall(alchemy_gpiochip_init); 134