1 /* 2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org> 3 * GPIOLIB support for Alchemy chips. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, write to the Free Software Foundation, Inc., 23 * 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * Notes : 26 * au1000 SoC have only one GPIO block : GPIO1 27 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 28 * Au1300 is totally different: 1 block with up to 128 GPIOs 29 */ 30 31 #include <linux/init.h> 32 #include <linux/kernel.h> 33 #include <linux/property.h> 34 #include <linux/types.h> 35 #include <linux/gpio/driver.h> 36 #include <asm/mach-au1x00/gpio-au1000.h> 37 #include <asm/mach-au1x00/gpio-au1300.h> 38 39 static int gpio2_get(struct gpio_chip *chip, unsigned offset) 40 { 41 return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); 42 } 43 44 static int gpio2_set(struct gpio_chip *chip, unsigned offset, int value) 45 { 46 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); 47 48 return 0; 49 } 50 51 static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset) 52 { 53 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); 54 } 55 56 static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset, 57 int value) 58 { 59 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, 60 value); 61 } 62 63 static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) 64 { 65 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); 66 } 67 68 69 static int gpio1_get(struct gpio_chip *chip, unsigned offset) 70 { 71 return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE); 72 } 73 74 static int gpio1_set(struct gpio_chip *chip, 75 unsigned offset, int value) 76 { 77 alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value); 78 79 return 0; 80 } 81 82 static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset) 83 { 84 return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE); 85 } 86 87 static int gpio1_direction_output(struct gpio_chip *chip, 88 unsigned offset, int value) 89 { 90 return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE, 91 value); 92 } 93 94 static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset) 95 { 96 return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE); 97 } 98 99 const struct software_node alchemy_gpio1_node = { 100 .name = "alchemy-gpio1", 101 }; 102 103 const struct software_node alchemy_gpio2_node = { 104 .name = "alchemy-gpio2", 105 }; 106 107 const struct software_node alchemy_gpic_node = { 108 .name = "alchemy-gpic", 109 }; 110 111 static const struct software_node *alchemy_gpio_node_group[] = { 112 &alchemy_gpio1_node, 113 &alchemy_gpio2_node, 114 &alchemy_gpic_node, 115 NULL 116 }; 117 118 static struct gpio_chip alchemy_gpio_chip[] = { 119 [0] = { 120 .label = "alchemy-gpio1", 121 .direction_input = gpio1_direction_input, 122 .direction_output = gpio1_direction_output, 123 .get = gpio1_get, 124 .set = gpio1_set, 125 .to_irq = gpio1_to_irq, 126 .base = ALCHEMY_GPIO1_BASE, 127 .ngpio = ALCHEMY_GPIO1_NUM, 128 }, 129 [1] = { 130 .label = "alchemy-gpio2", 131 .direction_input = gpio2_direction_input, 132 .direction_output = gpio2_direction_output, 133 .get = gpio2_get, 134 .set = gpio2_set, 135 .to_irq = gpio2_to_irq, 136 .base = ALCHEMY_GPIO2_BASE, 137 .ngpio = ALCHEMY_GPIO2_NUM, 138 }, 139 }; 140 141 static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off) 142 { 143 return !!au1300_gpio_get_value(off + AU1300_GPIO_BASE); 144 } 145 146 static int alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v) 147 { 148 au1300_gpio_set_value(off + AU1300_GPIO_BASE, v); 149 150 return 0; 151 } 152 153 static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off) 154 { 155 return au1300_gpio_direction_input(off + AU1300_GPIO_BASE); 156 } 157 158 static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off, 159 int v) 160 { 161 return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v); 162 } 163 164 static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off) 165 { 166 return au1300_gpio_to_irq(off + AU1300_GPIO_BASE); 167 } 168 169 static struct gpio_chip au1300_gpiochip = { 170 .label = "alchemy-gpic", 171 .direction_input = alchemy_gpic_dir_input, 172 .direction_output = alchemy_gpic_dir_output, 173 .get = alchemy_gpic_get, 174 .set = alchemy_gpic_set, 175 .to_irq = alchemy_gpic_gpio_to_irq, 176 .base = AU1300_GPIO_BASE, 177 .ngpio = AU1300_GPIO_NUM, 178 }; 179 180 /* 181 * Software nodes must be registered before board-specific code (that runs 182 * at arch_initcall level) attempts to use them as GPIO targets or as fwnodes 183 * for registered devices. We can not do registration in alchemy_gpiochip_init 184 * because it also runs as arch_initcall and runs after board-specific code 185 * because of the link order, and so we do it at postcore_initcall level. 186 */ 187 static int __init alchemy_gpio_nodes_init(void) 188 { 189 int ret; 190 191 ret = software_node_register_node_group(alchemy_gpio_node_group); 192 if (ret) 193 return ret; 194 195 alchemy_gpio_chip[0].fwnode = software_node_fwnode(&alchemy_gpio1_node); 196 alchemy_gpio_chip[1].fwnode = software_node_fwnode(&alchemy_gpio2_node); 197 au1300_gpiochip.fwnode = software_node_fwnode(&alchemy_gpic_node); 198 199 return 0; 200 } 201 postcore_initcall(alchemy_gpio_nodes_init); 202 203 static int __init alchemy_gpiochip_init(void) 204 { 205 int ret = 0; 206 207 switch (alchemy_get_cputype()) { 208 case ALCHEMY_CPU_AU1000: 209 ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL); 210 break; 211 case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200: 212 ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL); 213 ret |= gpiochip_add_data(&alchemy_gpio_chip[1], NULL); 214 break; 215 case ALCHEMY_CPU_AU1300: 216 ret = gpiochip_add_data(&au1300_gpiochip, NULL); 217 break; 218 } 219 return ret; 220 } 221 arch_initcall(alchemy_gpiochip_init); 222