1 /* 2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org> 3 * GPIOLIB support for Alchemy chips. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, write to the Free Software Foundation, Inc., 23 * 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * Notes : 26 * au1000 SoC have only one GPIO block : GPIO1 27 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 28 * Au1300 is totally different: 1 block with up to 128 GPIOs 29 */ 30 31 #include <linux/init.h> 32 #include <linux/kernel.h> 33 #include <linux/types.h> 34 #include <linux/gpio/driver.h> 35 #include <asm/mach-au1x00/gpio-au1000.h> 36 #include <asm/mach-au1x00/gpio-au1300.h> 37 38 static int gpio2_get(struct gpio_chip *chip, unsigned offset) 39 { 40 return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); 41 } 42 43 static int gpio2_set(struct gpio_chip *chip, unsigned offset, int value) 44 { 45 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); 46 47 return 0; 48 } 49 50 static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset) 51 { 52 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); 53 } 54 55 static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset, 56 int value) 57 { 58 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, 59 value); 60 } 61 62 static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) 63 { 64 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); 65 } 66 67 68 static int gpio1_get(struct gpio_chip *chip, unsigned offset) 69 { 70 return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE); 71 } 72 73 static int gpio1_set(struct gpio_chip *chip, 74 unsigned offset, int value) 75 { 76 alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value); 77 78 return 0; 79 } 80 81 static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset) 82 { 83 return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE); 84 } 85 86 static int gpio1_direction_output(struct gpio_chip *chip, 87 unsigned offset, int value) 88 { 89 return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE, 90 value); 91 } 92 93 static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset) 94 { 95 return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE); 96 } 97 98 struct gpio_chip alchemy_gpio_chip[] = { 99 [0] = { 100 .label = "alchemy-gpio1", 101 .direction_input = gpio1_direction_input, 102 .direction_output = gpio1_direction_output, 103 .get = gpio1_get, 104 .set = gpio1_set, 105 .to_irq = gpio1_to_irq, 106 .base = ALCHEMY_GPIO1_BASE, 107 .ngpio = ALCHEMY_GPIO1_NUM, 108 }, 109 [1] = { 110 .label = "alchemy-gpio2", 111 .direction_input = gpio2_direction_input, 112 .direction_output = gpio2_direction_output, 113 .get = gpio2_get, 114 .set = gpio2_set, 115 .to_irq = gpio2_to_irq, 116 .base = ALCHEMY_GPIO2_BASE, 117 .ngpio = ALCHEMY_GPIO2_NUM, 118 }, 119 }; 120 121 static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off) 122 { 123 return !!au1300_gpio_get_value(off + AU1300_GPIO_BASE); 124 } 125 126 static int alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v) 127 { 128 au1300_gpio_set_value(off + AU1300_GPIO_BASE, v); 129 130 return 0; 131 } 132 133 static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off) 134 { 135 return au1300_gpio_direction_input(off + AU1300_GPIO_BASE); 136 } 137 138 static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off, 139 int v) 140 { 141 return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v); 142 } 143 144 static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off) 145 { 146 return au1300_gpio_to_irq(off + AU1300_GPIO_BASE); 147 } 148 149 static struct gpio_chip au1300_gpiochip = { 150 .label = "alchemy-gpic", 151 .direction_input = alchemy_gpic_dir_input, 152 .direction_output = alchemy_gpic_dir_output, 153 .get = alchemy_gpic_get, 154 .set = alchemy_gpic_set, 155 .to_irq = alchemy_gpic_gpio_to_irq, 156 .base = AU1300_GPIO_BASE, 157 .ngpio = AU1300_GPIO_NUM, 158 }; 159 160 static int __init alchemy_gpiochip_init(void) 161 { 162 int ret = 0; 163 164 switch (alchemy_get_cputype()) { 165 case ALCHEMY_CPU_AU1000: 166 ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL); 167 break; 168 case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200: 169 ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL); 170 ret |= gpiochip_add_data(&alchemy_gpio_chip[1], NULL); 171 break; 172 case ALCHEMY_CPU_AU1300: 173 ret = gpiochip_add_data(&au1300_gpiochip, NULL); 174 break; 175 } 176 return ret; 177 } 178 arch_initcall(alchemy_gpiochip_init); 179