1 /* 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2012-2013 Xilinx, Inc. 4 * Copyright (C) 2007-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/sched.h> 15 #include <linux/sched_clock.h> 16 #include <linux/clk.h> 17 #include <linux/clockchips.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <asm/cpuinfo.h> 21 22 static void __iomem *timer_baseaddr; 23 24 static unsigned int freq_div_hz; 25 static unsigned int timer_clock_freq; 26 27 #define TCSR0 (0x00) 28 #define TLR0 (0x04) 29 #define TCR0 (0x08) 30 #define TCSR1 (0x10) 31 #define TLR1 (0x14) 32 #define TCR1 (0x18) 33 34 #define TCSR_MDT (1<<0) 35 #define TCSR_UDT (1<<1) 36 #define TCSR_GENT (1<<2) 37 #define TCSR_CAPT (1<<3) 38 #define TCSR_ARHT (1<<4) 39 #define TCSR_LOAD (1<<5) 40 #define TCSR_ENIT (1<<6) 41 #define TCSR_ENT (1<<7) 42 #define TCSR_TINT (1<<8) 43 #define TCSR_PWMA (1<<9) 44 #define TCSR_ENALL (1<<10) 45 46 static unsigned int (*read_fn)(void __iomem *); 47 static void (*write_fn)(u32, void __iomem *); 48 49 static void timer_write32(u32 val, void __iomem *addr) 50 { 51 iowrite32(val, addr); 52 } 53 54 static unsigned int timer_read32(void __iomem *addr) 55 { 56 return ioread32(addr); 57 } 58 59 static void timer_write32_be(u32 val, void __iomem *addr) 60 { 61 iowrite32be(val, addr); 62 } 63 64 static unsigned int timer_read32_be(void __iomem *addr) 65 { 66 return ioread32be(addr); 67 } 68 69 static inline void xilinx_timer0_stop(void) 70 { 71 write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT, 72 timer_baseaddr + TCSR0); 73 } 74 75 static inline void xilinx_timer0_start_periodic(unsigned long load_val) 76 { 77 if (!load_val) 78 load_val = 1; 79 /* loading value to timer reg */ 80 write_fn(load_val, timer_baseaddr + TLR0); 81 82 /* load the initial value */ 83 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0); 84 85 /* see timer data sheet for detail 86 * !ENALL - don't enable 'em all 87 * !PWMA - disable pwm 88 * TINT - clear interrupt status 89 * ENT- enable timer itself 90 * ENIT - enable interrupt 91 * !LOAD - clear the bit to let go 92 * ARHT - auto reload 93 * !CAPT - no external trigger 94 * !GENT - no external signal 95 * UDT - set the timer as down counter 96 * !MDT0 - generate mode 97 */ 98 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT, 99 timer_baseaddr + TCSR0); 100 } 101 102 static inline void xilinx_timer0_start_oneshot(unsigned long load_val) 103 { 104 if (!load_val) 105 load_val = 1; 106 /* loading value to timer reg */ 107 write_fn(load_val, timer_baseaddr + TLR0); 108 109 /* load the initial value */ 110 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0); 111 112 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT, 113 timer_baseaddr + TCSR0); 114 } 115 116 static int xilinx_timer_set_next_event(unsigned long delta, 117 struct clock_event_device *dev) 118 { 119 pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); 120 xilinx_timer0_start_oneshot(delta); 121 return 0; 122 } 123 124 static void xilinx_timer_set_mode(enum clock_event_mode mode, 125 struct clock_event_device *evt) 126 { 127 switch (mode) { 128 case CLOCK_EVT_MODE_PERIODIC: 129 pr_info("%s: periodic\n", __func__); 130 xilinx_timer0_start_periodic(freq_div_hz); 131 break; 132 case CLOCK_EVT_MODE_ONESHOT: 133 pr_info("%s: oneshot\n", __func__); 134 break; 135 case CLOCK_EVT_MODE_UNUSED: 136 pr_info("%s: unused\n", __func__); 137 break; 138 case CLOCK_EVT_MODE_SHUTDOWN: 139 pr_info("%s: shutdown\n", __func__); 140 xilinx_timer0_stop(); 141 break; 142 case CLOCK_EVT_MODE_RESUME: 143 pr_info("%s: resume\n", __func__); 144 break; 145 } 146 } 147 148 static struct clock_event_device clockevent_xilinx_timer = { 149 .name = "xilinx_clockevent", 150 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 151 .shift = 8, 152 .rating = 300, 153 .set_next_event = xilinx_timer_set_next_event, 154 .set_mode = xilinx_timer_set_mode, 155 }; 156 157 static inline void timer_ack(void) 158 { 159 write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0); 160 } 161 162 static irqreturn_t timer_interrupt(int irq, void *dev_id) 163 { 164 struct clock_event_device *evt = &clockevent_xilinx_timer; 165 #ifdef CONFIG_HEART_BEAT 166 microblaze_heartbeat(); 167 #endif 168 timer_ack(); 169 evt->event_handler(evt); 170 return IRQ_HANDLED; 171 } 172 173 static struct irqaction timer_irqaction = { 174 .handler = timer_interrupt, 175 .flags = IRQF_TIMER, 176 .name = "timer", 177 .dev_id = &clockevent_xilinx_timer, 178 }; 179 180 static __init void xilinx_clockevent_init(void) 181 { 182 clockevent_xilinx_timer.mult = 183 div_sc(timer_clock_freq, NSEC_PER_SEC, 184 clockevent_xilinx_timer.shift); 185 clockevent_xilinx_timer.max_delta_ns = 186 clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer); 187 clockevent_xilinx_timer.min_delta_ns = 188 clockevent_delta2ns(1, &clockevent_xilinx_timer); 189 clockevent_xilinx_timer.cpumask = cpumask_of(0); 190 clockevents_register_device(&clockevent_xilinx_timer); 191 } 192 193 static u64 xilinx_clock_read(void) 194 { 195 return read_fn(timer_baseaddr + TCR1); 196 } 197 198 static cycle_t xilinx_read(struct clocksource *cs) 199 { 200 /* reading actual value of timer 1 */ 201 return (cycle_t)xilinx_clock_read(); 202 } 203 204 static struct timecounter xilinx_tc = { 205 .cc = NULL, 206 }; 207 208 static cycle_t xilinx_cc_read(const struct cyclecounter *cc) 209 { 210 return xilinx_read(NULL); 211 } 212 213 static struct cyclecounter xilinx_cc = { 214 .read = xilinx_cc_read, 215 .mask = CLOCKSOURCE_MASK(32), 216 .shift = 8, 217 }; 218 219 static int __init init_xilinx_timecounter(void) 220 { 221 xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, 222 xilinx_cc.shift); 223 224 timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock()); 225 226 return 0; 227 } 228 229 static struct clocksource clocksource_microblaze = { 230 .name = "xilinx_clocksource", 231 .rating = 300, 232 .read = xilinx_read, 233 .mask = CLOCKSOURCE_MASK(32), 234 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 235 }; 236 237 static int __init xilinx_clocksource_init(void) 238 { 239 if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq)) 240 panic("failed to register clocksource"); 241 242 /* stop timer1 */ 243 write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT, 244 timer_baseaddr + TCSR1); 245 /* start timer1 - up counting without interrupt */ 246 write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1); 247 248 /* register timecounter - for ftrace support */ 249 init_xilinx_timecounter(); 250 return 0; 251 } 252 253 static void __init xilinx_timer_init(struct device_node *timer) 254 { 255 struct clk *clk; 256 static int initialized; 257 u32 irq; 258 u32 timer_num = 1; 259 260 if (initialized) 261 return; 262 263 initialized = 1; 264 265 timer_baseaddr = of_iomap(timer, 0); 266 if (!timer_baseaddr) { 267 pr_err("ERROR: invalid timer base address\n"); 268 BUG(); 269 } 270 271 write_fn = timer_write32; 272 read_fn = timer_read32; 273 274 write_fn(TCSR_MDT, timer_baseaddr + TCSR0); 275 if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) { 276 write_fn = timer_write32_be; 277 read_fn = timer_read32_be; 278 } 279 280 irq = irq_of_parse_and_map(timer, 0); 281 282 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); 283 if (timer_num) { 284 pr_emerg("Please enable two timers in HW\n"); 285 BUG(); 286 } 287 288 pr_info("%s: irq=%d\n", timer->full_name, irq); 289 290 clk = of_clk_get(timer, 0); 291 if (IS_ERR(clk)) { 292 pr_err("ERROR: timer CCF input clock not found\n"); 293 /* If there is clock-frequency property than use it */ 294 of_property_read_u32(timer, "clock-frequency", 295 &timer_clock_freq); 296 } else { 297 timer_clock_freq = clk_get_rate(clk); 298 } 299 300 if (!timer_clock_freq) { 301 pr_err("ERROR: Using CPU clock frequency\n"); 302 timer_clock_freq = cpuinfo.cpu_clock_freq; 303 } 304 305 freq_div_hz = timer_clock_freq / HZ; 306 307 setup_irq(irq, &timer_irqaction); 308 #ifdef CONFIG_HEART_BEAT 309 microblaze_setup_heartbeat(); 310 #endif 311 xilinx_clocksource_init(); 312 xilinx_clockevent_init(); 313 314 sched_clock_register(xilinx_clock_read, 32, timer_clock_freq); 315 } 316 317 CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a", 318 xilinx_timer_init); 319