1/* 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2007-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * MMU code derived from arch/ppc/kernel/head_4xx.S: 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 8 * Initial PowerPC version. 9 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 10 * Rewritten for PReP 11 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 12 * Low-level exception handers, MMU support, and rewrite. 13 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 14 * PowerPC 8xx modifications. 15 * Copyright (c) 1998-1999 TiVo, Inc. 16 * PowerPC 403GCX modifications. 17 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 18 * PowerPC 403GCX/405GP modifications. 19 * Copyright 2000 MontaVista Software Inc. 20 * PPC405 modifications 21 * PowerPC 403GCX/405GP modifications. 22 * Author: MontaVista Software, Inc. 23 * frank_rowand@mvista.com or source@mvista.com 24 * debbie_chu@mvista.com 25 * 26 * This file is subject to the terms and conditions of the GNU General Public 27 * License. See the file "COPYING" in the main directory of this archive 28 * for more details. 29 */ 30 31#include <linux/init.h> 32#include <linux/linkage.h> 33#include <asm/thread_info.h> 34#include <asm/page.h> 35#include <linux/of_fdt.h> /* for OF_DT_HEADER */ 36 37#ifdef CONFIG_MMU 38#include <asm/setup.h> /* COMMAND_LINE_SIZE */ 39#include <asm/mmu.h> 40#include <asm/processor.h> 41 42.section .data 43.global empty_zero_page 44.align 12 45empty_zero_page: 46 .space PAGE_SIZE 47.global swapper_pg_dir 48swapper_pg_dir: 49 .space PAGE_SIZE 50 51#endif /* CONFIG_MMU */ 52 53.section .rodata 54.align 4 55endian_check: 56 .word 1 57 58 __HEAD 59ENTRY(_start) 60#if CONFIG_KERNEL_BASE_ADDR == 0 61 brai TOPHYS(real_start) 62 .org 0x100 63real_start: 64#endif 65 66 mts rmsr, r0 67/* 68 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' 69 * if the msrclr instruction is not enabled. We use this to detect 70 * if the opcode is available, by issuing msrclr and then testing the result. 71 * r8 == 0 - msr instructions are implemented 72 * r8 != 0 - msr instructions are not implemented 73 */ 74 mfs r1, rmsr 75 msrclr r8, 0 /* clear nothing - just read msr for test */ 76 cmpu r8, r8, r1 /* r1 must contain msr reg content */ 77 78/* r7 may point to an FDT, or there may be one linked in. 79 if it's in r7, we've got to save it away ASAP. 80 We ensure r7 points to a valid FDT, just in case the bootloader 81 is broken or non-existent */ 82 beqi r7, no_fdt_arg /* NULL pointer? don't copy */ 83/* Does r7 point to a valid FDT? Load HEADER magic number */ 84 /* Run time Big/Little endian platform */ 85 /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */ 86 lbui r11, r0, TOPHYS(endian_check) 87 beqid r11, big_endian /* DO NOT break delay stop dependency */ 88 lw r11, r0, r7 /* Big endian load in delay slot */ 89 lwr r11, r0, r7 /* Little endian load */ 90big_endian: 91 rsubi r11, r11, OF_DT_HEADER /* Check FDT header */ 92 beqi r11, _prepare_copy_fdt 93 or r7, r0, r0 /* clear R7 when not valid DTB */ 94 bnei r11, no_fdt_arg /* No - get out of here */ 95_prepare_copy_fdt: 96 or r11, r0, r0 /* incremment */ 97 ori r4, r0, TOPHYS(_fdt_start) 98 ori r3, r0, (0x8000 - 4) 99_copy_fdt: 100 lw r12, r7, r11 /* r12 = r7 + r11 */ 101 sw r12, r4, r11 /* addr[r4 + r11] = r12 */ 102 addik r11, r11, 4 /* increment counting */ 103 bgtid r3, _copy_fdt /* loop for all entries */ 104 addik r3, r3, -4 /* descrement loop */ 105no_fdt_arg: 106 107#ifdef CONFIG_MMU 108 109#ifndef CONFIG_CMDLINE_BOOL 110/* 111 * handling command line 112 * copy command line directly to cmd_line placed in data section. 113 */ 114 beqid r5, skip /* Skip if NULL pointer */ 115 or r11, r0, r0 /* incremment */ 116 ori r4, r0, cmd_line /* load address of command line */ 117 tophys(r4,r4) /* convert to phys address */ 118 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ 119_copy_command_line: 120 /* r2=r5+r6 - r5 contain pointer to command line */ 121 lbu r2, r5, r11 122 beqid r2, skip /* Skip if no data */ 123 sb r2, r4, r11 /* addr[r4+r6]= r2 */ 124 addik r11, r11, 1 /* increment counting */ 125 bgtid r3, _copy_command_line /* loop for all entries */ 126 addik r3, r3, -1 /* decrement loop */ 127 addik r5, r4, 0 /* add new space for command line */ 128 tovirt(r5,r5) 129skip: 130#endif /* CONFIG_CMDLINE_BOOL */ 131 132#ifdef NOT_COMPILE 133/* save bram context */ 134 or r11, r0, r0 /* incremment */ 135 ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */ 136 ori r3, r0, (LMB_SIZE - 4) 137_copy_bram: 138 lw r7, r0, r11 /* r7 = r0 + r6 */ 139 sw r7, r4, r11 /* addr[r4 + r6] = r7 */ 140 addik r11, r11, 4 /* increment counting */ 141 bgtid r3, _copy_bram /* loop for all entries */ 142 addik r3, r3, -4 /* descrement loop */ 143#endif 144 /* We have to turn on the MMU right away. */ 145 146 /* 147 * Set up the initial MMU state so we can do the first level of 148 * kernel initialization. This maps the first 16 MBytes of memory 1:1 149 * virtual to physical. 150 */ 151 nop 152 addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */ 153_invalidate: 154 mts rtlbx, r3 155 mts rtlbhi, r0 /* flush: ensure V is clear */ 156 mts rtlblo, r0 157 bgtid r3, _invalidate /* loop for all entries */ 158 addik r3, r3, -1 159 /* sync */ 160 161 /* Setup the kernel PID */ 162 mts rpid,r0 /* Load the kernel PID */ 163 nop 164 bri 4 165 166 /* 167 * We should still be executing code at physical address area 168 * RAM_BASEADDR at this point. However, kernel code is at 169 * a virtual address. So, set up a TLB mapping to cover this once 170 * translation is enabled. 171 */ 172 173 addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ 174 tophys(r4,r3) /* Load the kernel physical address */ 175 176 /* start to do TLB calculation */ 177 addik r12, r0, _end 178 rsub r12, r3, r12 179 addik r12, r12, CONFIG_LOWMEM_SIZE >> PTE_SHIFT /* that's the pad */ 180 181 or r9, r0, r0 /* TLB0 = 0 */ 182 or r10, r0, r0 /* TLB1 = 0 */ 183 184 addik r11, r12, -0x1000000 185 bgei r11, GT16 /* size is greater than 16MB */ 186 addik r11, r12, -0x0800000 187 bgei r11, GT8 /* size is greater than 8MB */ 188 addik r11, r12, -0x0400000 189 bgei r11, GT4 /* size is greater than 4MB */ 190 /* size is less than 4MB */ 191 addik r11, r12, -0x0200000 192 bgei r11, GT2 /* size is greater than 2MB */ 193 addik r9, r0, 0x0100000 /* TLB0 must be 1MB */ 194 addik r11, r12, -0x0100000 195 bgei r11, GT1 /* size is greater than 1MB */ 196 /* TLB1 is 0 which is setup above */ 197 bri tlb_end 198GT4: /* r11 contains the rest - will be either 1 or 4 */ 199 ori r9, r0, 0x400000 /* TLB0 is 4MB */ 200 bri TLB1 201GT16: /* TLB0 is 16MB */ 202 addik r9, r0, 0x1000000 /* means TLB0 is 16MB */ 203TLB1: 204 /* must be used r2 because of substract if failed */ 205 addik r2, r11, -0x0400000 206 bgei r2, GT20 /* size is greater than 16MB */ 207 /* size is >16MB and <20MB */ 208 addik r11, r11, -0x0100000 209 bgei r11, GT17 /* size is greater than 17MB */ 210 /* kernel is >16MB and < 17MB */ 211GT1: 212 addik r10, r0, 0x0100000 /* means TLB1 is 1MB */ 213 bri tlb_end 214GT2: /* TLB0 is 0 and TLB1 will be 4MB */ 215GT17: /* TLB1 is 4MB - kernel size <20MB */ 216 addik r10, r0, 0x0400000 /* means TLB1 is 4MB */ 217 bri tlb_end 218GT8: /* TLB0 is still zero that's why I can use only TLB1 */ 219GT20: /* TLB1 is 16MB - kernel size >20MB */ 220 addik r10, r0, 0x1000000 /* means TLB1 is 16MB */ 221tlb_end: 222 223 /* 224 * Configure and load two entries into TLB slots 0 and 1. 225 * In case we are pinning TLBs, these are reserved in by the 226 * other TLB functions. If not reserving, then it doesn't 227 * matter where they are loaded. 228 */ 229 andi r4,r4,0xfffffc00 /* Mask off the real page number */ 230 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 231 232 /* 233 * TLB0 is always used - check if is not zero (r9 stores TLB0 value) 234 * if is use TLB1 value and clear it (r10 stores TLB1 value) 235 */ 236 bnei r9, tlb0_not_zero 237 add r9, r10, r0 238 add r10, r0, r0 239tlb0_not_zero: 240 241 /* look at the code below */ 242 ori r30, r0, 0x200 243 andi r29, r9, 0x100000 244 bneid r29, 1f 245 addik r30, r30, 0x80 246 andi r29, r9, 0x400000 247 bneid r29, 1f 248 addik r30, r30, 0x80 249 andi r29, r9, 0x1000000 250 bneid r29, 1f 251 addik r30, r30, 0x80 2521: 253 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 254 ori r3,r3,(TLB_VALID) 255 or r3, r3, r30 256 257 /* Load tlb_skip size value which is index to first unused TLB entry */ 258 lwi r11, r0, TOPHYS(tlb_skip) 259 mts rtlbx,r11 /* TLB slow 0 */ 260 261 mts rtlblo,r4 /* Load the data portion of the entry */ 262 mts rtlbhi,r3 /* Load the tag portion of the entry */ 263 264 /* Increase tlb_skip size */ 265 addik r11, r11, 1 266 swi r11, r0, TOPHYS(tlb_skip) 267 268 /* TLB1 can be zeroes that's why we not setup it */ 269 beqi r10, jump_over2 270 271 /* look at the code below */ 272 ori r30, r0, 0x200 273 andi r29, r10, 0x100000 274 bneid r29, 1f 275 addik r30, r30, 0x80 276 andi r29, r10, 0x400000 277 bneid r29, 1f 278 addik r30, r30, 0x80 279 andi r29, r10, 0x1000000 280 bneid r29, 1f 281 addik r30, r30, 0x80 2821: 283 addk r4, r4, r9 /* previous addr + TLB0 size */ 284 addk r3, r3, r9 285 286 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 287 ori r3,r3,(TLB_VALID) 288 or r3, r3, r30 289 290 lwi r11, r0, TOPHYS(tlb_skip) 291 mts rtlbx, r11 /* r11 is used from TLB0 */ 292 293 mts rtlblo,r4 /* Load the data portion of the entry */ 294 mts rtlbhi,r3 /* Load the tag portion of the entry */ 295 296 /* Increase tlb_skip size */ 297 addik r11, r11, 1 298 swi r11, r0, TOPHYS(tlb_skip) 299 300jump_over2: 301 /* 302 * Load a TLB entry for LMB, since we need access to 303 * the exception vectors, using a 4k real==virtual mapping. 304 */ 305 /* Use temporary TLB_ID for LMB - clear this temporary mapping later */ 306 ori r11, r0, MICROBLAZE_LMB_TLB_ID 307 mts rtlbx,r11 308 309 ori r4,r0,(TLB_WR | TLB_EX) 310 ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) 311 312 mts rtlblo,r4 /* Load the data portion of the entry */ 313 mts rtlbhi,r3 /* Load the tag portion of the entry */ 314 315 /* 316 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the 317 * caches ready to work. 318 */ 319turn_on_mmu: 320 ori r15,r0,start_here 321 ori r4,r0,MSR_KERNEL_VMS 322 mts rmsr,r4 323 nop 324 rted r15,0 /* enables MMU */ 325 nop 326 327start_here: 328#endif /* CONFIG_MMU */ 329 330 /* Initialize small data anchors */ 331 addik r13, r0, _KERNEL_SDA_BASE_ 332 addik r2, r0, _KERNEL_SDA2_BASE_ 333 334 /* Initialize stack pointer */ 335 addik r1, r0, init_thread_union + THREAD_SIZE - 4 336 337 /* Initialize r31 with current task address */ 338 addik r31, r0, init_task 339 340 /* 341 * Call platform dependent initialize function. 342 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for 343 * the function. 344 */ 345 addik r11, r0, machine_early_init 346 brald r15, r11 347 nop 348 349#ifndef CONFIG_MMU 350 addik r15, r0, machine_halt 351 braid start_kernel 352 nop 353#else 354 /* 355 * Initialize the MMU. 356 */ 357 bralid r15, mmu_init 358 nop 359 360 /* Go back to running unmapped so we can load up new values 361 * and change to using our exception vectors. 362 * On the MicroBlaze, all we invalidate the used TLB entries to clear 363 * the old 16M byte TLB mappings. 364 */ 365 ori r15,r0,TOPHYS(kernel_load_context) 366 ori r4,r0,MSR_KERNEL 367 mts rmsr,r4 368 nop 369 bri 4 370 rted r15,0 371 nop 372 373 /* Load up the kernel context */ 374kernel_load_context: 375 ori r5, r0, MICROBLAZE_LMB_TLB_ID 376 mts rtlbx,r5 377 nop 378 mts rtlbhi,r0 379 nop 380 addi r15, r0, machine_halt 381 ori r17, r0, start_kernel 382 ori r4, r0, MSR_KERNEL_VMS 383 mts rmsr, r4 384 nop 385 rted r17, 0 /* enable MMU and jump to start_kernel */ 386 nop 387#endif /* CONFIG_MMU */ 388