1/* 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2007-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * MMU code derived from arch/ppc/kernel/head_4xx.S: 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 8 * Initial PowerPC version. 9 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 10 * Rewritten for PReP 11 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 12 * Low-level exception handers, MMU support, and rewrite. 13 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 14 * PowerPC 8xx modifications. 15 * Copyright (c) 1998-1999 TiVo, Inc. 16 * PowerPC 403GCX modifications. 17 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 18 * PowerPC 403GCX/405GP modifications. 19 * Copyright 2000 MontaVista Software Inc. 20 * PPC405 modifications 21 * PowerPC 403GCX/405GP modifications. 22 * Author: MontaVista Software, Inc. 23 * frank_rowand@mvista.com or source@mvista.com 24 * debbie_chu@mvista.com 25 * 26 * This file is subject to the terms and conditions of the GNU General Public 27 * License. See the file "COPYING" in the main directory of this archive 28 * for more details. 29 */ 30 31#include <linux/init.h> 32#include <linux/linkage.h> 33#include <asm/thread_info.h> 34#include <asm/page.h> 35#include <linux/of_fdt.h> /* for OF_DT_HEADER */ 36 37#include <asm/setup.h> /* COMMAND_LINE_SIZE */ 38#include <asm/mmu.h> 39#include <asm/processor.h> 40 41.section .data 42/* The MMU requires a page aligned page directory. */ 43.align 12 44.global swapper_pg_dir 45swapper_pg_dir: 46 .space PAGE_SIZE 47 48.section .rodata 49.align 4 50endian_check: 51 .word 1 52 53 __HEAD 54ENTRY(_start) 55#if CONFIG_KERNEL_BASE_ADDR == 0 56 brai TOPHYS(real_start) 57 .org 0x100 58real_start: 59#endif 60 61 mts rmsr, r0 62/* Disable stack protection from bootloader */ 63 mts rslr, r0 64 addi r8, r0, 0xFFFFFFFF 65 mts rshr, r8 66/* 67 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' 68 * if the msrclr instruction is not enabled. We use this to detect 69 * if the opcode is available, by issuing msrclr and then testing the result. 70 * r8 == 0 - msr instructions are implemented 71 * r8 != 0 - msr instructions are not implemented 72 */ 73 mfs r1, rmsr 74 msrclr r8, 0 /* clear nothing - just read msr for test */ 75 cmpu r8, r8, r1 /* r1 must contain msr reg content */ 76 77/* r7 may point to an FDT, or there may be one linked in. 78 if it's in r7, we've got to save it away ASAP. 79 We ensure r7 points to a valid FDT, just in case the bootloader 80 is broken or non-existent */ 81 beqi r7, no_fdt_arg /* NULL pointer? don't copy */ 82/* Does r7 point to a valid FDT? Load HEADER magic number */ 83 /* Run time Big/Little endian platform */ 84 /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */ 85 lbui r11, r0, TOPHYS(endian_check) 86 beqid r11, big_endian /* DO NOT break delay stop dependency */ 87 lw r11, r0, r7 /* Big endian load in delay slot */ 88 lwr r11, r0, r7 /* Little endian load */ 89big_endian: 90 rsubi r11, r11, OF_DT_HEADER /* Check FDT header */ 91 beqi r11, _prepare_copy_fdt 92 or r7, r0, r0 /* clear R7 when not valid DTB */ 93 bnei r11, no_fdt_arg /* No - get out of here */ 94_prepare_copy_fdt: 95 or r11, r0, r0 /* incremment */ 96 ori r4, r0, TOPHYS(_fdt_start) 97 ori r3, r0, (0x10000 - 4) 98_copy_fdt: 99 lw r12, r7, r11 /* r12 = r7 + r11 */ 100 sw r12, r4, r11 /* addr[r4 + r11] = r12 */ 101 addik r11, r11, 4 /* increment counting */ 102 bgtid r3, _copy_fdt /* loop for all entries */ 103 addik r3, r3, -4 /* descrement loop */ 104no_fdt_arg: 105 106#ifndef CONFIG_CMDLINE_BOOL 107/* 108 * handling command line 109 * copy command line directly to cmd_line placed in data section. 110 */ 111 beqid r5, skip /* Skip if NULL pointer */ 112 or r11, r0, r0 /* incremment */ 113 ori r4, r0, cmd_line /* load address of command line */ 114 tophys(r4,r4) /* convert to phys address */ 115 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ 116_copy_command_line: 117 /* r2=r5+r11 - r5 contain pointer to command line */ 118 lbu r2, r5, r11 119 beqid r2, skip /* Skip if no data */ 120 sb r2, r4, r11 /* addr[r4+r11]= r2 */ 121 addik r11, r11, 1 /* increment counting */ 122 bgtid r3, _copy_command_line /* loop for all entries */ 123 addik r3, r3, -1 /* decrement loop */ 124 addik r5, r4, 0 /* add new space for command line */ 125 tovirt(r5,r5) 126skip: 127#endif /* CONFIG_CMDLINE_BOOL */ 128 129#ifdef NOT_COMPILE 130/* save bram context */ 131 or r11, r0, r0 /* incremment */ 132 ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */ 133 ori r3, r0, (LMB_SIZE - 4) 134_copy_bram: 135 lw r7, r0, r11 /* r7 = r0 + r11 */ 136 sw r7, r4, r11 /* addr[r4 + r11] = r7 */ 137 addik r11, r11, 4 /* increment counting */ 138 bgtid r3, _copy_bram /* loop for all entries */ 139 addik r3, r3, -4 /* descrement loop */ 140#endif 141 /* We have to turn on the MMU right away. */ 142 143 /* 144 * Set up the initial MMU state so we can do the first level of 145 * kernel initialization. This maps the first 16 MBytes of memory 1:1 146 * virtual to physical. 147 */ 148 nop 149 addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */ 150_invalidate: 151 mts rtlbx, r3 152 mts rtlbhi, r0 /* flush: ensure V is clear */ 153 mts rtlblo, r0 154 bgtid r3, _invalidate /* loop for all entries */ 155 addik r3, r3, -1 156 /* sync */ 157 158 /* Setup the kernel PID */ 159 mts rpid,r0 /* Load the kernel PID */ 160 nop 161 bri 4 162 163 /* 164 * We should still be executing code at physical address area 165 * RAM_BASEADDR at this point. However, kernel code is at 166 * a virtual address. So, set up a TLB mapping to cover this once 167 * translation is enabled. 168 */ 169 170 addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ 171 tophys(r4,r3) /* Load the kernel physical address */ 172 173 /* start to do TLB calculation */ 174 addik r12, r0, _end 175 rsub r12, r3, r12 176 addik r12, r12, CONFIG_LOWMEM_SIZE >> PTE_SHIFT /* that's the pad */ 177 178 or r9, r0, r0 /* TLB0 = 0 */ 179 or r10, r0, r0 /* TLB1 = 0 */ 180 181 addik r11, r12, -0x1000000 182 bgei r11, GT16 /* size is greater than 16MB */ 183 addik r11, r12, -0x0800000 184 bgei r11, GT8 /* size is greater than 8MB */ 185 addik r11, r12, -0x0400000 186 bgei r11, GT4 /* size is greater than 4MB */ 187 /* size is less than 4MB */ 188 addik r11, r12, -0x0200000 189 bgei r11, GT2 /* size is greater than 2MB */ 190 addik r9, r0, 0x0100000 /* TLB0 must be 1MB */ 191 addik r11, r12, -0x0100000 192 bgei r11, GT1 /* size is greater than 1MB */ 193 /* TLB1 is 0 which is setup above */ 194 bri tlb_end 195GT4: /* r11 contains the rest - will be either 1 or 4 */ 196 ori r9, r0, 0x400000 /* TLB0 is 4MB */ 197 bri TLB1 198GT16: /* TLB0 is 16MB */ 199 addik r9, r0, 0x1000000 /* means TLB0 is 16MB */ 200TLB1: 201 /* must be used r2 because of subtract if failed */ 202 addik r2, r11, -0x0400000 203 bgei r2, GT20 /* size is greater than 16MB */ 204 /* size is >16MB and <20MB */ 205 addik r11, r11, -0x0100000 206 bgei r11, GT17 /* size is greater than 17MB */ 207 /* kernel is >16MB and < 17MB */ 208GT1: 209 addik r10, r0, 0x0100000 /* means TLB1 is 1MB */ 210 bri tlb_end 211GT2: /* TLB0 is 0 and TLB1 will be 4MB */ 212GT17: /* TLB1 is 4MB - kernel size <20MB */ 213 addik r10, r0, 0x0400000 /* means TLB1 is 4MB */ 214 bri tlb_end 215GT8: /* TLB0 is still zero that's why I can use only TLB1 */ 216GT20: /* TLB1 is 16MB - kernel size >20MB */ 217 addik r10, r0, 0x1000000 /* means TLB1 is 16MB */ 218tlb_end: 219 220 /* 221 * Configure and load two entries into TLB slots 0 and 1. 222 * In case we are pinning TLBs, these are reserved in by the 223 * other TLB functions. If not reserving, then it doesn't 224 * matter where they are loaded. 225 */ 226 andi r4,r4,0xfffffc00 /* Mask off the real page number */ 227 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 228 229 /* 230 * TLB0 is always used - check if is not zero (r9 stores TLB0 value) 231 * if is use TLB1 value and clear it (r10 stores TLB1 value) 232 */ 233 bnei r9, tlb0_not_zero 234 add r9, r10, r0 235 add r10, r0, r0 236tlb0_not_zero: 237 238 /* look at the code below */ 239 ori r30, r0, 0x200 240 andi r29, r9, 0x100000 241 bneid r29, 1f 242 addik r30, r30, 0x80 243 andi r29, r9, 0x400000 244 bneid r29, 1f 245 addik r30, r30, 0x80 246 andi r29, r9, 0x1000000 247 bneid r29, 1f 248 addik r30, r30, 0x80 2491: 250 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 251 ori r3,r3,(TLB_VALID) 252 or r3, r3, r30 253 254 /* Load tlb_skip size value which is index to first unused TLB entry */ 255 lwi r11, r0, TOPHYS(tlb_skip) 256 mts rtlbx,r11 /* TLB slow 0 */ 257 258 mts rtlblo,r4 /* Load the data portion of the entry */ 259 mts rtlbhi,r3 /* Load the tag portion of the entry */ 260 261 /* Increase tlb_skip size */ 262 addik r11, r11, 1 263 swi r11, r0, TOPHYS(tlb_skip) 264 265 /* TLB1 can be zeroes that's why we not setup it */ 266 beqi r10, jump_over2 267 268 /* look at the code below */ 269 ori r30, r0, 0x200 270 andi r29, r10, 0x100000 271 bneid r29, 1f 272 addik r30, r30, 0x80 273 andi r29, r10, 0x400000 274 bneid r29, 1f 275 addik r30, r30, 0x80 276 andi r29, r10, 0x1000000 277 bneid r29, 1f 278 addik r30, r30, 0x80 2791: 280 addk r4, r4, r9 /* previous addr + TLB0 size */ 281 addk r3, r3, r9 282 283 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 284 ori r3,r3,(TLB_VALID) 285 or r3, r3, r30 286 287 lwi r11, r0, TOPHYS(tlb_skip) 288 mts rtlbx, r11 /* r11 is used from TLB0 */ 289 290 mts rtlblo,r4 /* Load the data portion of the entry */ 291 mts rtlbhi,r3 /* Load the tag portion of the entry */ 292 293 /* Increase tlb_skip size */ 294 addik r11, r11, 1 295 swi r11, r0, TOPHYS(tlb_skip) 296 297jump_over2: 298 /* 299 * Load a TLB entry for LMB, since we need access to 300 * the exception vectors, using a 4k real==virtual mapping. 301 */ 302 /* Use temporary TLB_ID for LMB - clear this temporary mapping later */ 303 ori r11, r0, MICROBLAZE_LMB_TLB_ID 304 mts rtlbx,r11 305 306 ori r4,r0,(TLB_WR | TLB_EX) 307 ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) 308 309 mts rtlblo,r4 /* Load the data portion of the entry */ 310 mts rtlbhi,r3 /* Load the tag portion of the entry */ 311 312 /* 313 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the 314 * caches ready to work. 315 */ 316turn_on_mmu: 317 ori r15,r0,start_here 318 ori r4,r0,MSR_KERNEL_VMS 319 mts rmsr,r4 320 nop 321 rted r15,0 /* enables MMU */ 322 nop 323 324start_here: 325 326 /* Initialize small data anchors */ 327 addik r13, r0, _KERNEL_SDA_BASE_ 328 addik r2, r0, _KERNEL_SDA2_BASE_ 329 330 /* Initialize stack pointer */ 331 addik r1, r0, init_thread_union + THREAD_SIZE - 4 332 333 /* Initialize r31 with current task address */ 334 addik r31, r0, init_task 335 336 addik r11, r0, machine_early_init 337 brald r15, r11 338 nop 339 340 /* 341 * Initialize the MMU. 342 */ 343 bralid r15, mmu_init 344 nop 345 346 /* Go back to running unmapped so we can load up new values 347 * and change to using our exception vectors. 348 * On the MicroBlaze, all we invalidate the used TLB entries to clear 349 * the old 16M byte TLB mappings. 350 */ 351 ori r15,r0,TOPHYS(kernel_load_context) 352 ori r4,r0,MSR_KERNEL 353 mts rmsr,r4 354 nop 355 bri 4 356 rted r15,0 357 nop 358 359 /* Load up the kernel context */ 360kernel_load_context: 361 ori r5, r0, MICROBLAZE_LMB_TLB_ID 362 mts rtlbx,r5 363 nop 364 mts rtlbhi,r0 365 nop 366 addi r15, r0, machine_halt 367 ori r17, r0, start_kernel 368 ori r4, r0, MSR_KERNEL_VMS 369 mts rmsr, r4 370 nop 371 rted r17, 0 /* enable MMU and jump to start_kernel */ 372 nop 373