1/* 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2007-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * MMU code derived from arch/ppc/kernel/head_4xx.S: 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 8 * Initial PowerPC version. 9 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 10 * Rewritten for PReP 11 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 12 * Low-level exception handers, MMU support, and rewrite. 13 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 14 * PowerPC 8xx modifications. 15 * Copyright (c) 1998-1999 TiVo, Inc. 16 * PowerPC 403GCX modifications. 17 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 18 * PowerPC 403GCX/405GP modifications. 19 * Copyright 2000 MontaVista Software Inc. 20 * PPC405 modifications 21 * PowerPC 403GCX/405GP modifications. 22 * Author: MontaVista Software, Inc. 23 * frank_rowand@mvista.com or source@mvista.com 24 * debbie_chu@mvista.com 25 * 26 * This file is subject to the terms and conditions of the GNU General Public 27 * License. See the file "COPYING" in the main directory of this archive 28 * for more details. 29 */ 30 31#include <linux/linkage.h> 32#include <asm/thread_info.h> 33#include <asm/page.h> 34#include <asm/prom.h> /* for OF_DT_HEADER */ 35 36#ifdef CONFIG_MMU 37#include <asm/setup.h> /* COMMAND_LINE_SIZE */ 38#include <asm/mmu.h> 39#include <asm/processor.h> 40 41.data 42.global empty_zero_page 43.align 12 44empty_zero_page: 45 .space 4096 46.global swapper_pg_dir 47swapper_pg_dir: 48 .space 4096 49 50#endif /* CONFIG_MMU */ 51 52 .text 53ENTRY(_start) 54 mfs r1, rmsr 55 andi r1, r1, ~2 56 mts rmsr, r1 57 58/* r7 may point to an FDT, or there may be one linked in. 59 if it's in r7, we've got to save it away ASAP. 60 We ensure r7 points to a valid FDT, just in case the bootloader 61 is broken or non-existent */ 62 beqi r7, no_fdt_arg /* NULL pointer? don't copy */ 63 lw r11, r0, r7 /* Does r7 point to a */ 64 rsubi r11, r11, OF_DT_HEADER /* valid FDT? */ 65 beqi r11, _prepare_copy_fdt 66 or r7, r0, r0 /* clear R7 when not valid DTB */ 67 bnei r11, no_fdt_arg /* No - get out of here */ 68_prepare_copy_fdt: 69 or r11, r0, r0 /* incremment */ 70 ori r4, r0, TOPHYS(_fdt_start) 71 ori r3, r0, (0x4000 - 4) 72_copy_fdt: 73 lw r12, r7, r11 /* r12 = r7 + r11 */ 74 sw r12, r4, r11 /* addr[r4 + r11] = r12 */ 75 addik r11, r11, 4 /* increment counting */ 76 bgtid r3, _copy_fdt /* loop for all entries */ 77 addik r3, r3, -4 /* descrement loop */ 78no_fdt_arg: 79 80#ifdef CONFIG_MMU 81 82#ifndef CONFIG_CMDLINE_BOOL 83/* 84 * handling command line 85 * copy command line to __init_end. There is space for storing command line. 86 */ 87 or r6, r0, r0 /* incremment */ 88 ori r4, r0, __init_end /* load address of command line */ 89 tophys(r4,r4) /* convert to phys address */ 90 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ 91_copy_command_line: 92 lbu r7, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */ 93 sb r7, r4, r6 /* addr[r4+r6]= r7*/ 94 addik r6, r6, 1 /* increment counting */ 95 bgtid r3, _copy_command_line /* loop for all entries */ 96 addik r3, r3, -1 /* descrement loop */ 97 addik r5, r4, 0 /* add new space for command line */ 98 tovirt(r5,r5) 99#endif /* CONFIG_CMDLINE_BOOL */ 100 101#ifdef NOT_COMPILE 102/* save bram context */ 103 or r6, r0, r0 /* incremment */ 104 ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */ 105 ori r3, r0, (LMB_SIZE - 4) 106_copy_bram: 107 lw r7, r0, r6 /* r7 = r0 + r6 */ 108 sw r7, r4, r6 /* addr[r4 + r6] = r7*/ 109 addik r6, r6, 4 /* increment counting */ 110 bgtid r3, _copy_bram /* loop for all entries */ 111 addik r3, r3, -4 /* descrement loop */ 112#endif 113 /* We have to turn on the MMU right away. */ 114 115 /* 116 * Set up the initial MMU state so we can do the first level of 117 * kernel initialization. This maps the first 16 MBytes of memory 1:1 118 * virtual to physical. 119 */ 120 nop 121 addik r3, r0, 63 /* Invalidate all TLB entries */ 122_invalidate: 123 mts rtlbx, r3 124 mts rtlbhi, r0 /* flush: ensure V is clear */ 125 bgtid r3, _invalidate /* loop for all entries */ 126 addik r3, r3, -1 127 /* sync */ 128 129 /* 130 * We should still be executing code at physical address area 131 * RAM_BASEADDR at this point. However, kernel code is at 132 * a virtual address. So, set up a TLB mapping to cover this once 133 * translation is enabled. 134 */ 135 136 addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ 137 tophys(r4,r3) /* Load the kernel physical address */ 138 139 mts rpid,r0 /* Load the kernel PID */ 140 nop 141 bri 4 142 143 /* 144 * Configure and load two entries into TLB slots 0 and 1. 145 * In case we are pinning TLBs, these are reserved in by the 146 * other TLB functions. If not reserving, then it doesn't 147 * matter where they are loaded. 148 */ 149 andi r4,r4,0xfffffc00 /* Mask off the real page number */ 150 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 151 152 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 153 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) 154 155 mts rtlbx,r0 /* TLB slow 0 */ 156 157 mts rtlblo,r4 /* Load the data portion of the entry */ 158 mts rtlbhi,r3 /* Load the tag portion of the entry */ 159 160 addik r4, r4, 0x01000000 /* Map next 16 M entries */ 161 addik r3, r3, 0x01000000 162 163 ori r6,r0,1 /* TLB slot 1 */ 164 mts rtlbx,r6 165 166 mts rtlblo,r4 /* Load the data portion of the entry */ 167 mts rtlbhi,r3 /* Load the tag portion of the entry */ 168 169 /* 170 * Load a TLB entry for LMB, since we need access to 171 * the exception vectors, using a 4k real==virtual mapping. 172 */ 173 ori r6,r0,3 /* TLB slot 3 */ 174 mts rtlbx,r6 175 176 ori r4,r0,(TLB_WR | TLB_EX) 177 ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) 178 179 mts rtlblo,r4 /* Load the data portion of the entry */ 180 mts rtlbhi,r3 /* Load the tag portion of the entry */ 181 182 /* 183 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the 184 * caches ready to work. 185 */ 186turn_on_mmu: 187 ori r15,r0,start_here 188 ori r4,r0,MSR_KERNEL_VMS 189 mts rmsr,r4 190 nop 191 rted r15,0 /* enables MMU */ 192 nop 193 194start_here: 195#endif /* CONFIG_MMU */ 196 197 /* Initialize small data anchors */ 198 la r13, r0, _KERNEL_SDA_BASE_ 199 la r2, r0, _KERNEL_SDA2_BASE_ 200 201 /* Initialize stack pointer */ 202 la r1, r0, init_thread_union + THREAD_SIZE - 4 203 204 /* Initialize r31 with current task address */ 205 la r31, r0, init_task 206 207 /* 208 * Call platform dependent initialize function. 209 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for 210 * the function. 211 */ 212 la r8, r0, machine_early_init 213 brald r15, r8 214 nop 215 216#ifndef CONFIG_MMU 217 la r15, r0, machine_halt 218 braid start_kernel 219 nop 220#else 221 /* 222 * Initialize the MMU. 223 */ 224 bralid r15, mmu_init 225 nop 226 227 /* Go back to running unmapped so we can load up new values 228 * and change to using our exception vectors. 229 * On the MicroBlaze, all we invalidate the used TLB entries to clear 230 * the old 16M byte TLB mappings. 231 */ 232 ori r15,r0,TOPHYS(kernel_load_context) 233 ori r4,r0,MSR_KERNEL 234 mts rmsr,r4 235 nop 236 bri 4 237 rted r15,0 238 nop 239 240 /* Load up the kernel context */ 241kernel_load_context: 242 # Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away. 243 ori r5,r0,3 244 mts rtlbx,r5 245 nop 246 mts rtlbhi,r0 247 nop 248 addi r15, r0, machine_halt 249 ori r17, r0, start_kernel 250 ori r4, r0, MSR_KERNEL_VMS 251 mts rmsr, r4 252 nop 253 rted r17, 0 /* enable MMU and jump to start_kernel */ 254 nop 255#endif /* CONFIG_MMU */ 256