1*b0c62724SMichal Simek /* 2*b0c62724SMichal Simek * Support for the MicroBlaze PVR (Processor Version Register) 3*b0c62724SMichal Simek * 4*b0c62724SMichal Simek * Copyright (C) 2009 Michal Simek <monstr@monstr.eu> 5*b0c62724SMichal Simek * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 6*b0c62724SMichal Simek * Copyright (C) 2007 - 2009 PetaLogix 7*b0c62724SMichal Simek * 8*b0c62724SMichal Simek * This file is subject to the terms and conditions of the GNU General 9*b0c62724SMichal Simek * Public License. See the file COPYING in the main directory of this 10*b0c62724SMichal Simek * archive for more details. 11*b0c62724SMichal Simek */ 12*b0c62724SMichal Simek 13*b0c62724SMichal Simek #ifndef _ASM_MICROBLAZE_PVR_H 14*b0c62724SMichal Simek #define _ASM_MICROBLAZE_PVR_H 15*b0c62724SMichal Simek 16*b0c62724SMichal Simek #define PVR_MSR_BIT 0x400 17*b0c62724SMichal Simek 18*b0c62724SMichal Simek struct pvr_s { 19*b0c62724SMichal Simek unsigned pvr[16]; 20*b0c62724SMichal Simek }; 21*b0c62724SMichal Simek 22*b0c62724SMichal Simek /* The following taken from Xilinx's standalone BSP pvr.h */ 23*b0c62724SMichal Simek 24*b0c62724SMichal Simek /* Basic PVR mask */ 25*b0c62724SMichal Simek #define PVR0_PVR_FULL_MASK 0x80000000 26*b0c62724SMichal Simek #define PVR0_USE_BARREL_MASK 0x40000000 27*b0c62724SMichal Simek #define PVR0_USE_DIV_MASK 0x20000000 28*b0c62724SMichal Simek #define PVR0_USE_HW_MUL_MASK 0x10000000 29*b0c62724SMichal Simek #define PVR0_USE_FPU_MASK 0x08000000 30*b0c62724SMichal Simek #define PVR0_USE_EXC_MASK 0x04000000 31*b0c62724SMichal Simek #define PVR0_USE_ICACHE_MASK 0x02000000 32*b0c62724SMichal Simek #define PVR0_USE_DCACHE_MASK 0x01000000 33*b0c62724SMichal Simek #define PVR0_USE_MMU 0x00800000 /* new */ 34*b0c62724SMichal Simek #define PVR0_VERSION_MASK 0x0000FF00 35*b0c62724SMichal Simek #define PVR0_USER1_MASK 0x000000FF 36*b0c62724SMichal Simek 37*b0c62724SMichal Simek /* User 2 PVR mask */ 38*b0c62724SMichal Simek #define PVR1_USER2_MASK 0xFFFFFFFF 39*b0c62724SMichal Simek 40*b0c62724SMichal Simek /* Configuration PVR masks */ 41*b0c62724SMichal Simek #define PVR2_D_OPB_MASK 0x80000000 42*b0c62724SMichal Simek #define PVR2_D_LMB_MASK 0x40000000 43*b0c62724SMichal Simek #define PVR2_I_OPB_MASK 0x20000000 44*b0c62724SMichal Simek #define PVR2_I_LMB_MASK 0x10000000 45*b0c62724SMichal Simek #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 46*b0c62724SMichal Simek #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 47*b0c62724SMichal Simek #define PVR2_D_PLB_MASK 0x02000000 /* new */ 48*b0c62724SMichal Simek #define PVR2_I_PLB_MASK 0x01000000 /* new */ 49*b0c62724SMichal Simek #define PVR2_INTERCONNECT 0x00800000 /* new */ 50*b0c62724SMichal Simek #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 51*b0c62724SMichal Simek #define PVR2_USE_FSL_EXC 0x00040000 /* new */ 52*b0c62724SMichal Simek #define PVR2_USE_MSR_INSTR 0x00020000 53*b0c62724SMichal Simek #define PVR2_USE_PCMP_INSTR 0x00010000 54*b0c62724SMichal Simek #define PVR2_AREA_OPTIMISED 0x00008000 55*b0c62724SMichal Simek #define PVR2_USE_BARREL_MASK 0x00004000 56*b0c62724SMichal Simek #define PVR2_USE_DIV_MASK 0x00002000 57*b0c62724SMichal Simek #define PVR2_USE_HW_MUL_MASK 0x00001000 58*b0c62724SMichal Simek #define PVR2_USE_FPU_MASK 0x00000800 59*b0c62724SMichal Simek #define PVR2_USE_MUL64_MASK 0x00000400 60*b0c62724SMichal Simek #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 61*b0c62724SMichal Simek #define PVR2_USE_IPLBEXC 0x00000100 62*b0c62724SMichal Simek #define PVR2_USE_DPLBEXC 0x00000080 63*b0c62724SMichal Simek #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 64*b0c62724SMichal Simek #define PVR2_UNALIGNED_EXC_MASK 0x00000020 65*b0c62724SMichal Simek #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 66*b0c62724SMichal Simek #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 67*b0c62724SMichal Simek #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 68*b0c62724SMichal Simek #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 69*b0c62724SMichal Simek #define PVR2_FPU_EXC_MASK 0x00000001 70*b0c62724SMichal Simek 71*b0c62724SMichal Simek /* Debug and exception PVR masks */ 72*b0c62724SMichal Simek #define PVR3_DEBUG_ENABLED_MASK 0x80000000 73*b0c62724SMichal Simek #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 74*b0c62724SMichal Simek #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 75*b0c62724SMichal Simek #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 76*b0c62724SMichal Simek #define PVR3_FSL_LINKS_MASK 0x00000380 77*b0c62724SMichal Simek 78*b0c62724SMichal Simek /* ICache config PVR masks */ 79*b0c62724SMichal Simek #define PVR4_USE_ICACHE_MASK 0x80000000 80*b0c62724SMichal Simek #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 81*b0c62724SMichal Simek #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 82*b0c62724SMichal Simek #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 83*b0c62724SMichal Simek #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 84*b0c62724SMichal Simek #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 85*b0c62724SMichal Simek 86*b0c62724SMichal Simek /* DCache config PVR masks */ 87*b0c62724SMichal Simek #define PVR5_USE_DCACHE_MASK 0x80000000 88*b0c62724SMichal Simek #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 89*b0c62724SMichal Simek #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 90*b0c62724SMichal Simek #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 91*b0c62724SMichal Simek #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 92*b0c62724SMichal Simek #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 93*b0c62724SMichal Simek 94*b0c62724SMichal Simek /* ICache base address PVR mask */ 95*b0c62724SMichal Simek #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF 96*b0c62724SMichal Simek 97*b0c62724SMichal Simek /* ICache high address PVR mask */ 98*b0c62724SMichal Simek #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF 99*b0c62724SMichal Simek 100*b0c62724SMichal Simek /* DCache base address PVR mask */ 101*b0c62724SMichal Simek #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF 102*b0c62724SMichal Simek 103*b0c62724SMichal Simek /* DCache high address PVR mask */ 104*b0c62724SMichal Simek #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF 105*b0c62724SMichal Simek 106*b0c62724SMichal Simek /* Target family PVR mask */ 107*b0c62724SMichal Simek #define PVR10_TARGET_FAMILY_MASK 0xFF000000 108*b0c62724SMichal Simek 109*b0c62724SMichal Simek /* MMU descrtiption */ 110*b0c62724SMichal Simek #define PVR11_USE_MMU 0xC0000000 111*b0c62724SMichal Simek #define PVR11_MMU_ITLB_SIZE 0x38000000 112*b0c62724SMichal Simek #define PVR11_MMU_DTLB_SIZE 0x07000000 113*b0c62724SMichal Simek #define PVR11_MMU_TLB_ACCESS 0x00C00000 114*b0c62724SMichal Simek #define PVR11_MMU_ZONES 0x003C0000 115*b0c62724SMichal Simek /* MSR Reset value PVR mask */ 116*b0c62724SMichal Simek #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF 117*b0c62724SMichal Simek 118*b0c62724SMichal Simek 119*b0c62724SMichal Simek /* PVR access macros */ 120*b0c62724SMichal Simek #define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK) 121*b0c62724SMichal Simek #define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK) 122*b0c62724SMichal Simek #define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK) 123*b0c62724SMichal Simek #define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) 124*b0c62724SMichal Simek #define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK) 125*b0c62724SMichal Simek #define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK) 126*b0c62724SMichal Simek #define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK) 127*b0c62724SMichal Simek #define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK) 128*b0c62724SMichal Simek #define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) 129*b0c62724SMichal Simek #define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK) 130*b0c62724SMichal Simek #define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK) 131*b0c62724SMichal Simek 132*b0c62724SMichal Simek #define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK) 133*b0c62724SMichal Simek #define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK) 134*b0c62724SMichal Simek #define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK) 135*b0c62724SMichal Simek #define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK) 136*b0c62724SMichal Simek #define PVR_INTERRUPT_IS_EDGE(pvr) \ 137*b0c62724SMichal Simek (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) 138*b0c62724SMichal Simek #define PVR_EDGE_IS_POSITIVE(pvr) \ 139*b0c62724SMichal Simek (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) 140*b0c62724SMichal Simek #define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR) 141*b0c62724SMichal Simek #define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR) 142*b0c62724SMichal Simek #define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED) 143*b0c62724SMichal Simek #define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK) 144*b0c62724SMichal Simek #define PVR_OPCODE_0x0_ILLEGAL(pvr) \ 145*b0c62724SMichal Simek (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) 146*b0c62724SMichal Simek #define PVR_UNALIGNED_EXCEPTION(pvr) \ 147*b0c62724SMichal Simek (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) 148*b0c62724SMichal Simek #define PVR_ILL_OPCODE_EXCEPTION(pvr) \ 149*b0c62724SMichal Simek (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) 150*b0c62724SMichal Simek #define PVR_IOPB_BUS_EXCEPTION(pvr) \ 151*b0c62724SMichal Simek (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) 152*b0c62724SMichal Simek #define PVR_DOPB_BUS_EXCEPTION(pvr) \ 153*b0c62724SMichal Simek (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) 154*b0c62724SMichal Simek #define PVR_DIV_ZERO_EXCEPTION(pvr) \ 155*b0c62724SMichal Simek (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) 156*b0c62724SMichal Simek #define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK) 157*b0c62724SMichal Simek #define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL) 158*b0c62724SMichal Simek 159*b0c62724SMichal Simek #define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) 160*b0c62724SMichal Simek #define PVR_NUMBER_OF_PC_BRK(pvr) \ 161*b0c62724SMichal Simek ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) 162*b0c62724SMichal Simek #define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \ 163*b0c62724SMichal Simek ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) 164*b0c62724SMichal Simek #define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \ 165*b0c62724SMichal Simek ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) 166*b0c62724SMichal Simek #define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) 167*b0c62724SMichal Simek 168*b0c62724SMichal Simek #define PVR_ICACHE_ADDR_TAG_BITS(pvr) \ 169*b0c62724SMichal Simek ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) 170*b0c62724SMichal Simek #define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) 171*b0c62724SMichal Simek #define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) 172*b0c62724SMichal Simek #define PVR_ICACHE_LINE_LEN(pvr) \ 173*b0c62724SMichal Simek (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) 174*b0c62724SMichal Simek #define PVR_ICACHE_BYTE_SIZE(pvr) \ 175*b0c62724SMichal Simek (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) 176*b0c62724SMichal Simek 177*b0c62724SMichal Simek #define PVR_DCACHE_ADDR_TAG_BITS(pvr) \ 178*b0c62724SMichal Simek ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) 179*b0c62724SMichal Simek #define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) 180*b0c62724SMichal Simek #define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) 181*b0c62724SMichal Simek #define PVR_DCACHE_LINE_LEN(pvr) \ 182*b0c62724SMichal Simek (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) 183*b0c62724SMichal Simek #define PVR_DCACHE_BYTE_SIZE(pvr) \ 184*b0c62724SMichal Simek (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) 185*b0c62724SMichal Simek 186*b0c62724SMichal Simek 187*b0c62724SMichal Simek #define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) 188*b0c62724SMichal Simek #define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) 189*b0c62724SMichal Simek 190*b0c62724SMichal Simek #define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) 191*b0c62724SMichal Simek #define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) 192*b0c62724SMichal Simek 193*b0c62724SMichal Simek #define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) 194*b0c62724SMichal Simek 195*b0c62724SMichal Simek #define PVR_MSR_RESET_VALUE(pvr) \ 196*b0c62724SMichal Simek (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK) 197*b0c62724SMichal Simek 198*b0c62724SMichal Simek /* mmu */ 199*b0c62724SMichal Simek #define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30) 200*b0c62724SMichal Simek #define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) 201*b0c62724SMichal Simek #define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) 202*b0c62724SMichal Simek #define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) 203*b0c62724SMichal Simek #define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES) 204*b0c62724SMichal Simek 205*b0c62724SMichal Simek 206*b0c62724SMichal Simek int cpu_has_pvr(void); 207*b0c62724SMichal Simek void get_pvr(struct pvr_s *pvr); 208*b0c62724SMichal Simek 209*b0c62724SMichal Simek #endif /* _ASM_MICROBLAZE_PVR_H */ 210