1b0c62724SMichal Simek /* 2b0c62724SMichal Simek * Support for the MicroBlaze PVR (Processor Version Register) 3b0c62724SMichal Simek * 4b0c62724SMichal Simek * Copyright (C) 2009 Michal Simek <monstr@monstr.eu> 5b0c62724SMichal Simek * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 6b0c62724SMichal Simek * Copyright (C) 2007 - 2009 PetaLogix 7b0c62724SMichal Simek * 8b0c62724SMichal Simek * This file is subject to the terms and conditions of the GNU General 9b0c62724SMichal Simek * Public License. See the file COPYING in the main directory of this 10b0c62724SMichal Simek * archive for more details. 11b0c62724SMichal Simek */ 12b0c62724SMichal Simek 13b0c62724SMichal Simek #ifndef _ASM_MICROBLAZE_PVR_H 14b0c62724SMichal Simek #define _ASM_MICROBLAZE_PVR_H 15b0c62724SMichal Simek 16b0c62724SMichal Simek #define PVR_MSR_BIT 0x400 17b0c62724SMichal Simek 18b0c62724SMichal Simek struct pvr_s { 19*aee04d76SMichal Simek unsigned pvr[12]; 20b0c62724SMichal Simek }; 21b0c62724SMichal Simek 22b0c62724SMichal Simek /* The following taken from Xilinx's standalone BSP pvr.h */ 23b0c62724SMichal Simek 24b0c62724SMichal Simek /* Basic PVR mask */ 25b0c62724SMichal Simek #define PVR0_PVR_FULL_MASK 0x80000000 26b0c62724SMichal Simek #define PVR0_USE_BARREL_MASK 0x40000000 27b0c62724SMichal Simek #define PVR0_USE_DIV_MASK 0x20000000 28b0c62724SMichal Simek #define PVR0_USE_HW_MUL_MASK 0x10000000 29b0c62724SMichal Simek #define PVR0_USE_FPU_MASK 0x08000000 30b0c62724SMichal Simek #define PVR0_USE_EXC_MASK 0x04000000 31b0c62724SMichal Simek #define PVR0_USE_ICACHE_MASK 0x02000000 32b0c62724SMichal Simek #define PVR0_USE_DCACHE_MASK 0x01000000 33b0c62724SMichal Simek #define PVR0_USE_MMU 0x00800000 /* new */ 34b0c62724SMichal Simek #define PVR0_VERSION_MASK 0x0000FF00 35b0c62724SMichal Simek #define PVR0_USER1_MASK 0x000000FF 36b0c62724SMichal Simek 37b0c62724SMichal Simek /* User 2 PVR mask */ 38b0c62724SMichal Simek #define PVR1_USER2_MASK 0xFFFFFFFF 39b0c62724SMichal Simek 40b0c62724SMichal Simek /* Configuration PVR masks */ 41b0c62724SMichal Simek #define PVR2_D_OPB_MASK 0x80000000 42b0c62724SMichal Simek #define PVR2_D_LMB_MASK 0x40000000 43b0c62724SMichal Simek #define PVR2_I_OPB_MASK 0x20000000 44b0c62724SMichal Simek #define PVR2_I_LMB_MASK 0x10000000 45b0c62724SMichal Simek #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 46b0c62724SMichal Simek #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 47b0c62724SMichal Simek #define PVR2_D_PLB_MASK 0x02000000 /* new */ 48b0c62724SMichal Simek #define PVR2_I_PLB_MASK 0x01000000 /* new */ 49b0c62724SMichal Simek #define PVR2_INTERCONNECT 0x00800000 /* new */ 50b0c62724SMichal Simek #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 51b0c62724SMichal Simek #define PVR2_USE_FSL_EXC 0x00040000 /* new */ 52b0c62724SMichal Simek #define PVR2_USE_MSR_INSTR 0x00020000 53b0c62724SMichal Simek #define PVR2_USE_PCMP_INSTR 0x00010000 54b0c62724SMichal Simek #define PVR2_AREA_OPTIMISED 0x00008000 55b0c62724SMichal Simek #define PVR2_USE_BARREL_MASK 0x00004000 56b0c62724SMichal Simek #define PVR2_USE_DIV_MASK 0x00002000 57b0c62724SMichal Simek #define PVR2_USE_HW_MUL_MASK 0x00001000 58b0c62724SMichal Simek #define PVR2_USE_FPU_MASK 0x00000800 59b0c62724SMichal Simek #define PVR2_USE_MUL64_MASK 0x00000400 60b0c62724SMichal Simek #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 61b0c62724SMichal Simek #define PVR2_USE_IPLBEXC 0x00000100 62b0c62724SMichal Simek #define PVR2_USE_DPLBEXC 0x00000080 63b0c62724SMichal Simek #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 64b0c62724SMichal Simek #define PVR2_UNALIGNED_EXC_MASK 0x00000020 65b0c62724SMichal Simek #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 66b0c62724SMichal Simek #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 67b0c62724SMichal Simek #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 68b0c62724SMichal Simek #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 69b0c62724SMichal Simek #define PVR2_FPU_EXC_MASK 0x00000001 70b0c62724SMichal Simek 71b0c62724SMichal Simek /* Debug and exception PVR masks */ 72b0c62724SMichal Simek #define PVR3_DEBUG_ENABLED_MASK 0x80000000 73b0c62724SMichal Simek #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 74b0c62724SMichal Simek #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 75b0c62724SMichal Simek #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 76b0c62724SMichal Simek #define PVR3_FSL_LINKS_MASK 0x00000380 77b0c62724SMichal Simek 78b0c62724SMichal Simek /* ICache config PVR masks */ 79f6e1f1b4SMichal Simek #define PVR4_USE_ICACHE_MASK 0x80000000 /* ICU */ 80f6e1f1b4SMichal Simek #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* ICTS */ 81f6e1f1b4SMichal Simek #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 /* ICW */ 82f6e1f1b4SMichal Simek #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */ 83f6e1f1b4SMichal Simek #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */ 84f6e1f1b4SMichal Simek #define PVR4_ICACHE_ALWAYS_USED 0x00008000 /* IAU */ 85f6e1f1b4SMichal Simek #define PVR4_ICACHE_INTERFACE 0x00002000 /* ICI */ 86b0c62724SMichal Simek 87b0c62724SMichal Simek /* DCache config PVR masks */ 88f6e1f1b4SMichal Simek #define PVR5_USE_DCACHE_MASK 0x80000000 /* DCU */ 89f6e1f1b4SMichal Simek #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* DCTS */ 90f6e1f1b4SMichal Simek #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 /* DCW */ 91f6e1f1b4SMichal Simek #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */ 92f6e1f1b4SMichal Simek #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */ 93f6e1f1b4SMichal Simek #define PVR5_DCACHE_ALWAYS_USED 0x00008000 /* DAU */ 94f6e1f1b4SMichal Simek #define PVR5_DCACHE_USE_WRITEBACK 0x00004000 /* DWB */ 95f6e1f1b4SMichal Simek #define PVR5_DCACHE_INTERFACE 0x00002000 /* DCI */ 96b0c62724SMichal Simek 97b0c62724SMichal Simek /* ICache base address PVR mask */ 98b0c62724SMichal Simek #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF 99b0c62724SMichal Simek 100b0c62724SMichal Simek /* ICache high address PVR mask */ 101b0c62724SMichal Simek #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF 102b0c62724SMichal Simek 103b0c62724SMichal Simek /* DCache base address PVR mask */ 104b0c62724SMichal Simek #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF 105b0c62724SMichal Simek 106b0c62724SMichal Simek /* DCache high address PVR mask */ 107b0c62724SMichal Simek #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF 108b0c62724SMichal Simek 109b0c62724SMichal Simek /* Target family PVR mask */ 110b0c62724SMichal Simek #define PVR10_TARGET_FAMILY_MASK 0xFF000000 111b0c62724SMichal Simek 112b0c62724SMichal Simek /* MMU descrtiption */ 113b0c62724SMichal Simek #define PVR11_USE_MMU 0xC0000000 114b0c62724SMichal Simek #define PVR11_MMU_ITLB_SIZE 0x38000000 115b0c62724SMichal Simek #define PVR11_MMU_DTLB_SIZE 0x07000000 116b0c62724SMichal Simek #define PVR11_MMU_TLB_ACCESS 0x00C00000 117b0c62724SMichal Simek #define PVR11_MMU_ZONES 0x003C0000 118b0c62724SMichal Simek /* MSR Reset value PVR mask */ 119b0c62724SMichal Simek #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF 120b0c62724SMichal Simek 121b0c62724SMichal Simek 122b0c62724SMichal Simek /* PVR access macros */ 123b0c62724SMichal Simek #define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK) 124b0c62724SMichal Simek #define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK) 125b0c62724SMichal Simek #define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK) 126b0c62724SMichal Simek #define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) 127b0c62724SMichal Simek #define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK) 128b0c62724SMichal Simek #define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK) 129b0c62724SMichal Simek #define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK) 130b0c62724SMichal Simek #define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK) 131b0c62724SMichal Simek #define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) 132b0c62724SMichal Simek #define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK) 133b0c62724SMichal Simek #define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK) 134b0c62724SMichal Simek 135b0c62724SMichal Simek #define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK) 136b0c62724SMichal Simek #define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK) 137b0c62724SMichal Simek #define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK) 138b0c62724SMichal Simek #define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK) 139b0c62724SMichal Simek #define PVR_INTERRUPT_IS_EDGE(pvr) \ 140b0c62724SMichal Simek (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) 141b0c62724SMichal Simek #define PVR_EDGE_IS_POSITIVE(pvr) \ 142b0c62724SMichal Simek (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) 143b0c62724SMichal Simek #define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR) 144b0c62724SMichal Simek #define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR) 145b0c62724SMichal Simek #define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED) 146b0c62724SMichal Simek #define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK) 147b0c62724SMichal Simek #define PVR_OPCODE_0x0_ILLEGAL(pvr) \ 148b0c62724SMichal Simek (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) 149b0c62724SMichal Simek #define PVR_UNALIGNED_EXCEPTION(pvr) \ 150b0c62724SMichal Simek (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) 151b0c62724SMichal Simek #define PVR_ILL_OPCODE_EXCEPTION(pvr) \ 152b0c62724SMichal Simek (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) 153b0c62724SMichal Simek #define PVR_IOPB_BUS_EXCEPTION(pvr) \ 154b0c62724SMichal Simek (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) 155b0c62724SMichal Simek #define PVR_DOPB_BUS_EXCEPTION(pvr) \ 156b0c62724SMichal Simek (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) 157b0c62724SMichal Simek #define PVR_DIV_ZERO_EXCEPTION(pvr) \ 158b0c62724SMichal Simek (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) 159b0c62724SMichal Simek #define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK) 160b0c62724SMichal Simek #define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL) 161b0c62724SMichal Simek 162b0c62724SMichal Simek #define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) 163b0c62724SMichal Simek #define PVR_NUMBER_OF_PC_BRK(pvr) \ 164b0c62724SMichal Simek ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) 165b0c62724SMichal Simek #define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \ 166b0c62724SMichal Simek ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) 167b0c62724SMichal Simek #define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \ 168b0c62724SMichal Simek ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) 169b0c62724SMichal Simek #define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) 170b0c62724SMichal Simek 171b0c62724SMichal Simek #define PVR_ICACHE_ADDR_TAG_BITS(pvr) \ 172b0c62724SMichal Simek ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) 173b0c62724SMichal Simek #define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) 174b0c62724SMichal Simek #define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) 175b0c62724SMichal Simek #define PVR_ICACHE_LINE_LEN(pvr) \ 176b0c62724SMichal Simek (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) 177b0c62724SMichal Simek #define PVR_ICACHE_BYTE_SIZE(pvr) \ 178b0c62724SMichal Simek (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) 179b0c62724SMichal Simek 180b0c62724SMichal Simek #define PVR_DCACHE_ADDR_TAG_BITS(pvr) \ 181b0c62724SMichal Simek ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) 182b0c62724SMichal Simek #define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) 183b0c62724SMichal Simek #define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) 184f6e1f1b4SMichal Simek /* FIXME two shifts on one line needs any comment */ 185b0c62724SMichal Simek #define PVR_DCACHE_LINE_LEN(pvr) \ 186b0c62724SMichal Simek (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) 187b0c62724SMichal Simek #define PVR_DCACHE_BYTE_SIZE(pvr) \ 188b0c62724SMichal Simek (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) 189b0c62724SMichal Simek 190f6e1f1b4SMichal Simek #define PVR_DCACHE_USE_WRITEBACK(pvr) \ 191f6e1f1b4SMichal Simek ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) 192b0c62724SMichal Simek 193b0c62724SMichal Simek #define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) 194b0c62724SMichal Simek #define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) 195b0c62724SMichal Simek 196b0c62724SMichal Simek #define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) 197b0c62724SMichal Simek #define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) 198b0c62724SMichal Simek 199b0c62724SMichal Simek #define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) 200b0c62724SMichal Simek 201b0c62724SMichal Simek #define PVR_MSR_RESET_VALUE(pvr) \ 202b0c62724SMichal Simek (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK) 203b0c62724SMichal Simek 204b0c62724SMichal Simek /* mmu */ 205b0c62724SMichal Simek #define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30) 206b0c62724SMichal Simek #define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) 207b0c62724SMichal Simek #define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) 208b0c62724SMichal Simek #define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) 209b0c62724SMichal Simek #define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES) 210b0c62724SMichal Simek 211b0c62724SMichal Simek 212b0c62724SMichal Simek int cpu_has_pvr(void); 213b0c62724SMichal Simek void get_pvr(struct pvr_s *pvr); 214b0c62724SMichal Simek 215b0c62724SMichal Simek #endif /* _ASM_MICROBLAZE_PVR_H */ 216