1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2008-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 */ 7 8 #ifndef _ASM_MICROBLAZE_PGTABLE_H 9 #define _ASM_MICROBLAZE_PGTABLE_H 10 11 #include <asm/setup.h> 12 13 #ifndef __ASSEMBLY__ 14 extern int mem_init_done; 15 #endif 16 17 #ifndef CONFIG_MMU 18 19 #define pgd_present(pgd) (1) /* pages are always present on non MMU */ 20 #define pgd_none(pgd) (0) 21 #define pgd_bad(pgd) (0) 22 #define pgd_clear(pgdp) 23 #define kern_addr_valid(addr) (1) 24 #define pmd_offset(a, b) ((void *) 0) 25 26 #define PAGE_NONE __pgprot(0) /* these mean nothing to non MMU */ 27 #define PAGE_SHARED __pgprot(0) /* these mean nothing to non MMU */ 28 #define PAGE_COPY __pgprot(0) /* these mean nothing to non MMU */ 29 #define PAGE_READONLY __pgprot(0) /* these mean nothing to non MMU */ 30 #define PAGE_KERNEL __pgprot(0) /* these mean nothing to non MMU */ 31 32 #define pgprot_noncached(x) (x) 33 #define pgprot_writecombine pgprot_noncached 34 #define pgprot_device pgprot_noncached 35 36 #define __swp_type(x) (0) 37 #define __swp_offset(x) (0) 38 #define __swp_entry(typ, off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) 39 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 40 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 41 42 #define ZERO_PAGE(vaddr) ({ BUG(); NULL; }) 43 44 #define swapper_pg_dir ((pgd_t *) NULL) 45 46 #define arch_enter_lazy_cpu_mode() do {} while (0) 47 48 #define pgprot_noncached_wc(prot) prot 49 50 /* 51 * All 32bit addresses are effectively valid for vmalloc... 52 * Sort of meaningless for non-VM targets. 53 */ 54 #define VMALLOC_START 0 55 #define VMALLOC_END 0xffffffff 56 57 #else /* CONFIG_MMU */ 58 59 #include <asm-generic/pgtable-nopmd.h> 60 61 #ifdef __KERNEL__ 62 #ifndef __ASSEMBLY__ 63 64 #include <linux/sched.h> 65 #include <linux/threads.h> 66 #include <asm/processor.h> /* For TASK_SIZE */ 67 #include <asm/mmu.h> 68 #include <asm/page.h> 69 70 #define FIRST_USER_ADDRESS 0UL 71 72 extern unsigned long va_to_phys(unsigned long address); 73 extern pte_t *va_to_pte(unsigned long address); 74 75 /* 76 * The following only work if pte_present() is true. 77 * Undefined behaviour if not.. 78 */ 79 80 static inline int pte_special(pte_t pte) { return 0; } 81 82 static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 83 84 /* Start and end of the vmalloc area. */ 85 /* Make sure to map the vmalloc area above the pinned kernel memory area 86 of 32Mb. */ 87 #define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE) 88 #define VMALLOC_END ioremap_bot 89 90 #endif /* __ASSEMBLY__ */ 91 92 /* 93 * Macro to mark a page protection value as "uncacheable". 94 */ 95 96 #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \ 97 _PAGE_WRITETHRU) 98 99 #define pgprot_noncached(prot) \ 100 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 101 _PAGE_NO_CACHE | _PAGE_GUARDED)) 102 103 #define pgprot_noncached_wc(prot) \ 104 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 105 _PAGE_NO_CACHE)) 106 107 /* 108 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 109 * table containing PTEs, together with a set of 16 segment registers, to 110 * define the virtual to physical address mapping. 111 * 112 * We use the hash table as an extended TLB, i.e. a cache of currently 113 * active mappings. We maintain a two-level page table tree, much 114 * like that used by the i386, for the sake of the Linux memory 115 * management code. Low-level assembler code in hashtable.S 116 * (procedure hash_page) is responsible for extracting ptes from the 117 * tree and putting them into the hash table when necessary, and 118 * updating the accessed and modified bits in the page table tree. 119 */ 120 121 /* 122 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 123 * instruction and data sides share a unified, 64-entry, semi-associative 124 * TLB which is maintained totally under software control. In addition, the 125 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative 126 * TLB which serves as a first level to the shared TLB. These two TLBs are 127 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions). 128 */ 129 130 /* 131 * The normal case is that PTEs are 32-bits and we have a 1-page 132 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 133 * 134 */ 135 136 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 137 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT) 138 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 139 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 140 141 /* 142 * entries per page directory level: our page-table tree is two-level, so 143 * we don't really have any PMD directory. 144 */ 145 #define PTRS_PER_PTE (1 << PTE_SHIFT) 146 #define PTRS_PER_PMD 1 147 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) 148 149 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 150 #define FIRST_USER_PGD_NR 0 151 152 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) 153 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) 154 155 #define pte_ERROR(e) \ 156 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \ 157 __FILE__, __LINE__, pte_val(e)) 158 #define pgd_ERROR(e) \ 159 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ 160 __FILE__, __LINE__, pgd_val(e)) 161 162 /* 163 * Bits in a linux-style PTE. These match the bits in the 164 * (hardware-defined) PTE as closely as possible. 165 */ 166 167 /* There are several potential gotchas here. The hardware TLBLO 168 * field looks like this: 169 * 170 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 171 * RPN..................... 0 0 EX WR ZSEL....... W I M G 172 * 173 * Where possible we make the Linux PTE bits match up with this 174 * 175 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can 176 * support down to 1k pages), this is done in the TLBMiss exception 177 * handler. 178 * - We use only zones 0 (for kernel pages) and 1 (for user pages) 179 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB 180 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct 181 * zone. 182 * - PRESENT *must* be in the bottom two bits because swap cache 183 * entries use the top 30 bits. Because 4xx doesn't support SMP 184 * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 185 * is cleared in the TLB miss handler before the TLB entry is loaded. 186 * - All other bits of the PTE are loaded into TLBLO without 187 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for 188 * software PTE bits. We actually use bits 21, 24, 25, and 189 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and 190 * PRESENT. 191 */ 192 193 /* Definitions for MicroBlaze. */ 194 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ 195 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ 196 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ 197 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ 198 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ 199 #define _PAGE_RW 0x040 /* software: Writes permitted */ 200 #define _PAGE_DIRTY 0x080 /* software: dirty page */ 201 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ 202 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ 203 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ 204 #define _PMD_PRESENT PAGE_MASK 205 206 /* 207 * Some bits are unused... 208 */ 209 #ifndef _PAGE_HASHPTE 210 #define _PAGE_HASHPTE 0 211 #endif 212 #ifndef _PTE_NONE_MASK 213 #define _PTE_NONE_MASK 0 214 #endif 215 #ifndef _PAGE_SHARED 216 #define _PAGE_SHARED 0 217 #endif 218 #ifndef _PAGE_EXEC 219 #define _PAGE_EXEC 0 220 #endif 221 222 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 223 224 /* 225 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware 226 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need 227 * to have it in the Linux PTE, and in fact the bit could be reused for 228 * another purpose. -- paulus. 229 */ 230 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) 231 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) 232 233 #define _PAGE_KERNEL \ 234 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC) 235 236 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) 237 238 #define PAGE_NONE __pgprot(_PAGE_BASE) 239 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 240 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 241 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 242 #define PAGE_SHARED_X \ 243 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 244 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 245 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 246 247 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 248 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED) 249 #define PAGE_KERNEL_CI __pgprot(_PAGE_IO) 250 251 /* 252 * We consider execute permission the same as read. 253 * Also, write permissions imply read permissions. 254 */ 255 #define __P000 PAGE_NONE 256 #define __P001 PAGE_READONLY_X 257 #define __P010 PAGE_COPY 258 #define __P011 PAGE_COPY_X 259 #define __P100 PAGE_READONLY 260 #define __P101 PAGE_READONLY_X 261 #define __P110 PAGE_COPY 262 #define __P111 PAGE_COPY_X 263 264 #define __S000 PAGE_NONE 265 #define __S001 PAGE_READONLY_X 266 #define __S010 PAGE_SHARED 267 #define __S011 PAGE_SHARED_X 268 #define __S100 PAGE_READONLY 269 #define __S101 PAGE_READONLY_X 270 #define __S110 PAGE_SHARED 271 #define __S111 PAGE_SHARED_X 272 273 #ifndef __ASSEMBLY__ 274 /* 275 * ZERO_PAGE is a global shared page that is always zero: used 276 * for zero-mapped memory areas etc.. 277 */ 278 extern unsigned long empty_zero_page[1024]; 279 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 280 281 #endif /* __ASSEMBLY__ */ 282 283 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) 284 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 285 #define pte_clear(mm, addr, ptep) \ 286 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) 287 288 #define pmd_none(pmd) (!pmd_val(pmd)) 289 #define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0) 290 #define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0) 291 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) 292 293 #define pte_page(x) (mem_map + (unsigned long) \ 294 ((pte_val(x) - memory_start) >> PAGE_SHIFT)) 295 #define PFN_SHIFT_OFFSET (PAGE_SHIFT) 296 297 #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) 298 299 #define pfn_pte(pfn, prot) \ 300 __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot)) 301 302 #ifndef __ASSEMBLY__ 303 /* 304 * The following only work if pte_present() is true. 305 * Undefined behaviour if not.. 306 */ 307 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } 308 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } 309 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 310 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 311 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 312 313 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } 314 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } 315 316 static inline pte_t pte_rdprotect(pte_t pte) \ 317 { pte_val(pte) &= ~_PAGE_USER; return pte; } 318 static inline pte_t pte_wrprotect(pte_t pte) \ 319 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } 320 static inline pte_t pte_exprotect(pte_t pte) \ 321 { pte_val(pte) &= ~_PAGE_EXEC; return pte; } 322 static inline pte_t pte_mkclean(pte_t pte) \ 323 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } 324 static inline pte_t pte_mkold(pte_t pte) \ 325 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 326 327 static inline pte_t pte_mkread(pte_t pte) \ 328 { pte_val(pte) |= _PAGE_USER; return pte; } 329 static inline pte_t pte_mkexec(pte_t pte) \ 330 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } 331 static inline pte_t pte_mkwrite(pte_t pte) \ 332 { pte_val(pte) |= _PAGE_RW; return pte; } 333 static inline pte_t pte_mkdirty(pte_t pte) \ 334 { pte_val(pte) |= _PAGE_DIRTY; return pte; } 335 static inline pte_t pte_mkyoung(pte_t pte) \ 336 { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 337 338 /* 339 * Conversion functions: convert a page and protection to a page entry, 340 * and a page entry and page directory to the page they refer to. 341 */ 342 343 static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot) 344 { 345 pte_t pte; 346 pte_val(pte) = physpage | pgprot_val(pgprot); 347 return pte; 348 } 349 350 #define mk_pte(page, pgprot) \ 351 ({ \ 352 pte_t pte; \ 353 pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \ 354 pgprot_val(pgprot); \ 355 pte; \ 356 }) 357 358 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 359 { 360 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); 361 return pte; 362 } 363 364 /* 365 * Atomic PTE updates. 366 * 367 * pte_update clears and sets bit atomically, and returns 368 * the old pte value. 369 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant 370 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits. 371 */ 372 static inline unsigned long pte_update(pte_t *p, unsigned long clr, 373 unsigned long set) 374 { 375 unsigned long flags, old, tmp; 376 377 raw_local_irq_save(flags); 378 379 __asm__ __volatile__( "lw %0, %2, r0 \n" 380 "andn %1, %0, %3 \n" 381 "or %1, %1, %4 \n" 382 "sw %1, %2, r0 \n" 383 : "=&r" (old), "=&r" (tmp) 384 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set) 385 : "cc"); 386 387 raw_local_irq_restore(flags); 388 389 return old; 390 } 391 392 /* 393 * set_pte stores a linux PTE into the linux page table. 394 */ 395 static inline void set_pte(struct mm_struct *mm, unsigned long addr, 396 pte_t *ptep, pte_t pte) 397 { 398 *ptep = pte; 399 } 400 401 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 402 pte_t *ptep, pte_t pte) 403 { 404 *ptep = pte; 405 } 406 407 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 408 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 409 unsigned long address, pte_t *ptep) 410 { 411 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; 412 } 413 414 static inline int ptep_test_and_clear_dirty(struct mm_struct *mm, 415 unsigned long addr, pte_t *ptep) 416 { 417 return (pte_update(ptep, \ 418 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; 419 } 420 421 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 422 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 423 unsigned long addr, pte_t *ptep) 424 { 425 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); 426 } 427 428 /*static inline void ptep_set_wrprotect(struct mm_struct *mm, 429 unsigned long addr, pte_t *ptep) 430 { 431 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); 432 }*/ 433 434 static inline void ptep_mkdirty(struct mm_struct *mm, 435 unsigned long addr, pte_t *ptep) 436 { 437 pte_update(ptep, 0, _PAGE_DIRTY); 438 } 439 440 /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/ 441 442 /* Convert pmd entry to page */ 443 /* our pmd entry is an effective address of pte table*/ 444 /* returns effective address of the pmd entry*/ 445 #define pmd_page_kernel(pmd) ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) 446 447 /* returns struct *page of the pmd entry*/ 448 #define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT)) 449 450 /* to find an entry in a kernel page-table-directory */ 451 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 452 453 /* to find an entry in a page-table-directory */ 454 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 455 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 456 457 /* Find an entry in the third-level page table.. */ 458 #define pte_index(address) \ 459 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 460 #define pte_offset_kernel(dir, addr) \ 461 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr)) 462 #define pte_offset_map(dir, addr) \ 463 ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr)) 464 465 #define pte_unmap(pte) kunmap_atomic(pte) 466 467 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 468 469 /* 470 * Encode and decode a swap entry. 471 * Note that the bits we use in a PTE for representing a swap entry 472 * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit 473 * (if used). -- paulus 474 */ 475 #define __swp_type(entry) ((entry).val & 0x3f) 476 #define __swp_offset(entry) ((entry).val >> 6) 477 #define __swp_entry(type, offset) \ 478 ((swp_entry_t) { (type) | ((offset) << 6) }) 479 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 }) 480 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 }) 481 482 extern unsigned long iopa(unsigned long addr); 483 484 /* Values for nocacheflag and cmode */ 485 /* These are not used by the APUS kernel_map, but prevents 486 * compilation errors. 487 */ 488 #define IOMAP_FULL_CACHING 0 489 #define IOMAP_NOCACHE_SER 1 490 #define IOMAP_NOCACHE_NONSER 2 491 #define IOMAP_NO_COPYBACK 3 492 493 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 494 #define kern_addr_valid(addr) (1) 495 496 void do_page_fault(struct pt_regs *regs, unsigned long address, 497 unsigned long error_code); 498 499 void mapin_ram(void); 500 int map_page(unsigned long va, phys_addr_t pa, int flags); 501 502 extern int mem_init_done; 503 504 asmlinkage void __init mmu_init(void); 505 506 void __init *early_get_page(void); 507 508 #endif /* __ASSEMBLY__ */ 509 #endif /* __KERNEL__ */ 510 511 #endif /* CONFIG_MMU */ 512 513 #ifndef __ASSEMBLY__ 514 #include <asm-generic/pgtable.h> 515 516 extern unsigned long ioremap_bot, ioremap_base; 517 518 void setup_memory(void); 519 #endif /* __ASSEMBLY__ */ 520 521 #endif /* _ASM_MICROBLAZE_PGTABLE_H */ 522