1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H 3 #define _ASM_MICROBLAZE_PCI_BRIDGE_H 4 #ifdef __KERNEL__ 5 /* 6 */ 7 #include <linux/pci.h> 8 #include <linux/list.h> 9 #include <linux/ioport.h> 10 11 struct device_node; 12 13 #ifdef CONFIG_PCI 14 extern struct list_head hose_list; 15 extern int pcibios_vaddr_is_ioport(void __iomem *address); 16 #else 17 static inline int pcibios_vaddr_is_ioport(void __iomem *address) 18 { 19 return 0; 20 } 21 #endif 22 23 /* 24 * Structure of a PCI controller (host bridge) 25 */ 26 struct pci_controller { 27 struct pci_bus *bus; 28 char is_dynamic; 29 struct device_node *dn; 30 struct list_head list_node; 31 struct device *parent; 32 33 int first_busno; 34 int last_busno; 35 36 int self_busno; 37 38 void __iomem *io_base_virt; 39 resource_size_t io_base_phys; 40 41 /* Some machines (PReP) have a non 1:1 mapping of 42 * the PCI memory space in the CPU bus space 43 */ 44 resource_size_t pci_mem_offset; 45 46 struct pci_ops *ops; 47 unsigned int __iomem *cfg_addr; 48 void __iomem *cfg_data; 49 50 /* 51 * Used for variants of PCI indirect handling and possible quirks: 52 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 53 * EXT_REG - provides access to PCI-e extended registers 54 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS 55 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 56 * to determine which bus number to match on when generating type0 57 * config cycles 58 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 59 * hanging if we don't have link and try to do config cycles to 60 * anything but the PHB. Only allow talking to the PHB if this is 61 * set. 62 * BIG_ENDIAN - cfg_addr is a big endian register 63 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs 64 * on the PLB4. Effectively disable MRM commands by setting this. 65 */ 66 #define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 67 #define INDIRECT_TYPE_EXT_REG 0x00000002 68 #define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 69 #define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 70 #define INDIRECT_TYPE_BIG_ENDIAN 0x00000010 71 #define INDIRECT_TYPE_BROKEN_MRM 0x00000020 72 u32 indirect_type; 73 74 /* Currently, we limit ourselves to 1 IO range and 3 mem 75 * ranges since the common pci_bus structure can't handle more 76 */ 77 struct resource io_resource; 78 struct resource mem_resources[3]; 79 int global_number; /* PCI domain number */ 80 }; 81 82 #ifdef CONFIG_PCI 83 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 84 { 85 return bus->sysdata; 86 } 87 88 static inline int isa_vaddr_is_ioport(void __iomem *address) 89 { 90 /* No specific ISA handling on ppc32 at this stage, it 91 * all goes through PCI 92 */ 93 return 0; 94 } 95 #endif /* CONFIG_PCI */ 96 97 extern void setup_indirect_pci(struct pci_controller *hose, 98 resource_size_t cfg_addr, 99 resource_size_t cfg_data, u32 flags); 100 101 /* Allocate & free a PCI host bridge structure */ 102 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 103 extern void pcibios_free_controller(struct pci_controller *phb); 104 105 #endif /* __KERNEL__ */ 106 #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */ 107