1 /* 2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2008-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #ifndef _ASM_MICROBLAZE_MMU_H 12 #define _ASM_MICROBLAZE_MMU_H 13 14 # ifndef CONFIG_MMU 15 # ifndef __ASSEMBLY__ 16 typedef struct { 17 struct vm_list_struct *vmlist; 18 unsigned long end_brk; 19 } mm_context_t; 20 # endif /* __ASSEMBLY__ */ 21 # else /* CONFIG_MMU */ 22 # ifdef __KERNEL__ 23 # ifndef __ASSEMBLY__ 24 25 /* Default "unsigned long" context */ 26 typedef unsigned long mm_context_t; 27 28 /* Hardware Page Table Entry */ 29 typedef struct _PTE { 30 unsigned long v:1; /* Entry is valid */ 31 unsigned long vsid:24; /* Virtual segment identifier */ 32 unsigned long h:1; /* Hash algorithm indicator */ 33 unsigned long api:6; /* Abbreviated page index */ 34 unsigned long rpn:20; /* Real (physical) page number */ 35 unsigned long :3; /* Unused */ 36 unsigned long r:1; /* Referenced */ 37 unsigned long c:1; /* Changed */ 38 unsigned long w:1; /* Write-thru cache mode */ 39 unsigned long i:1; /* Cache inhibited */ 40 unsigned long m:1; /* Memory coherence */ 41 unsigned long g:1; /* Guarded */ 42 unsigned long :1; /* Unused */ 43 unsigned long pp:2; /* Page protection */ 44 } PTE; 45 46 /* Values for PP (assumes Ks=0, Kp=1) */ 47 # define PP_RWXX 0 /* Supervisor read/write, User none */ 48 # define PP_RWRX 1 /* Supervisor read/write, User read */ 49 # define PP_RWRW 2 /* Supervisor read/write, User read/write */ 50 # define PP_RXRX 3 /* Supervisor read, User read */ 51 52 /* Segment Register */ 53 typedef struct _SEGREG { 54 unsigned long t:1; /* Normal or I/O type */ 55 unsigned long ks:1; /* Supervisor 'key' (normally 0) */ 56 unsigned long kp:1; /* User 'key' (normally 1) */ 57 unsigned long n:1; /* No-execute */ 58 unsigned long :4; /* Unused */ 59 unsigned long vsid:24; /* Virtual Segment Identifier */ 60 } SEGREG; 61 62 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ 63 extern void _tlbia(void); /* invalidate all TLB entries */ 64 # endif /* __ASSEMBLY__ */ 65 66 /* 67 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 68 * instruction and data sides share a unified, 64-entry, semi-associative 69 * TLB which is maintained totally under software control. In addition, the 70 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative 71 * TLB which serves as a first level to the shared TLB. These two TLBs are 72 * known as the UTLB and ITLB, respectively. 73 */ 74 75 # define MICROBLAZE_TLB_SIZE 64 76 77 /* 78 * TLB entries are defined by a "high" tag portion and a "low" data 79 * portion. The data portion is 32-bits. 80 * 81 * TLB entries are managed entirely under software control by reading, 82 * writing, and searching using the MTS and MFS instructions. 83 */ 84 85 # define TLB_LO 1 86 # define TLB_HI 0 87 # define TLB_DATA TLB_LO 88 # define TLB_TAG TLB_HI 89 90 /* Tag portion */ 91 # define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ 92 # define TLB_PAGESZ_MASK 0x00000380 93 # define TLB_PAGESZ(x) (((x) & 0x7) << 7) 94 # define PAGESZ_1K 0 95 # define PAGESZ_4K 1 96 # define PAGESZ_16K 2 97 # define PAGESZ_64K 3 98 # define PAGESZ_256K 4 99 # define PAGESZ_1M 5 100 # define PAGESZ_4M 6 101 # define PAGESZ_16M 7 102 # define TLB_VALID 0x00000040 /* Entry is valid */ 103 104 /* Data portion */ 105 # define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ 106 # define TLB_PERM_MASK 0x00000300 107 # define TLB_EX 0x00000200 /* Instruction execution allowed */ 108 # define TLB_WR 0x00000100 /* Writes permitted */ 109 # define TLB_ZSEL_MASK 0x000000F0 110 # define TLB_ZSEL(x) (((x) & 0xF) << 4) 111 # define TLB_ATTR_MASK 0x0000000F 112 # define TLB_W 0x00000008 /* Caching is write-through */ 113 # define TLB_I 0x00000004 /* Caching is inhibited */ 114 # define TLB_M 0x00000002 /* Memory is coherent */ 115 # define TLB_G 0x00000001 /* Memory is guarded from prefetch */ 116 117 # endif /* __KERNEL__ */ 118 # endif /* CONFIG_MMU */ 119 #endif /* _ASM_MICROBLAZE_MMU_H */ 120