1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/delay.h> 4 #include <linux/interrupt.h> 5 #include <linux/irq.h> 6 #include <linux/kernel.h> 7 #include <linux/sched.h> 8 #include <linux/sched/debug.h> 9 #include <linux/types.h> 10 #include <linux/ioport.h> 11 12 #include <asm/hwtest.h> 13 #include <asm/irq.h> 14 #include <asm/irq_regs.h> 15 #include <asm/virt.h> 16 17 #define GFPIC_REG_IRQ_PENDING 0x04 18 #define GFPIC_REG_IRQ_DISABLE_ALL 0x08 19 #define GFPIC_REG_IRQ_DISABLE 0x0c 20 #define GFPIC_REG_IRQ_ENABLE 0x10 21 22 extern void show_registers(struct pt_regs *regs); 23 24 static struct resource picres[6]; 25 static const char *picname[6] = { 26 "goldfish_pic.0", 27 "goldfish_pic.1", 28 "goldfish_pic.2", 29 "goldfish_pic.3", 30 "goldfish_pic.4", 31 "goldfish_pic.5" 32 }; 33 34 /* 35 * 6 goldfish-pic for CPU IRQ #1 to IRQ #6 36 * CPU IRQ #1 -> PIC #1 37 * IRQ #1 to IRQ #31 -> unused 38 * IRQ #32 -> goldfish-tty 39 * CPU IRQ #2 -> PIC #2 40 * IRQ #1 to IRQ #32 -> virtio-mmio from 1 to 32 41 * CPU IRQ #3 -> PIC #3 42 * IRQ #1 to IRQ #32 -> virtio-mmio from 33 to 64 43 * CPU IRQ #4 -> PIC #4 44 * IRQ #1 to IRQ #32 -> virtio-mmio from 65 to 96 45 * CPU IRQ #5 -> PIC #5 46 * IRQ #1 to IRQ #32 -> virtio-mmio from 97 to 128 47 * CPU IRQ #6 -> PIC #6 48 * IRQ #1 -> goldfish-timer 49 * IRQ #2 -> goldfish-rtc 50 * IRQ #3 to IRQ #32 -> unused 51 * CPU IRQ #7 -> NMI 52 */ 53 54 static u32 gfpic_read(int pic, int reg) 55 { 56 void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio + 57 pic * 0x1000); 58 59 return ioread32be(base + reg); 60 } 61 62 static void gfpic_write(u32 value, int pic, int reg) 63 { 64 void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio + 65 pic * 0x1000); 66 67 iowrite32be(value, base + reg); 68 } 69 70 #define GF_PIC(irq) ((irq - IRQ_USER) / 32) 71 #define GF_IRQ(irq) ((irq - IRQ_USER) % 32) 72 73 static void virt_irq_enable(struct irq_data *data) 74 { 75 gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq), 76 GFPIC_REG_IRQ_ENABLE); 77 } 78 79 static void virt_irq_disable(struct irq_data *data) 80 { 81 gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq), 82 GFPIC_REG_IRQ_DISABLE); 83 } 84 85 static unsigned int virt_irq_startup(struct irq_data *data) 86 { 87 virt_irq_enable(data); 88 return 0; 89 } 90 91 static irqreturn_t virt_nmi_handler(int irq, void *dev_id) 92 { 93 static int in_nmi; 94 95 if (READ_ONCE(in_nmi)) 96 return IRQ_HANDLED; 97 WRITE_ONCE(in_nmi, 1); 98 99 pr_warn("Non-Maskable Interrupt\n"); 100 show_registers(get_irq_regs()); 101 102 WRITE_ONCE(in_nmi, 0); 103 return IRQ_HANDLED; 104 } 105 106 static struct irq_chip virt_irq_chip = { 107 .name = "virt", 108 .irq_enable = virt_irq_enable, 109 .irq_disable = virt_irq_disable, 110 .irq_startup = virt_irq_startup, 111 .irq_shutdown = virt_irq_disable, 112 }; 113 114 static void goldfish_pic_irq(struct irq_desc *desc) 115 { 116 u32 irq_pending; 117 unsigned int irq_num; 118 unsigned int pic = desc->irq_data.irq - 1; 119 120 irq_pending = gfpic_read(pic, GFPIC_REG_IRQ_PENDING); 121 irq_num = IRQ_USER + pic * 32; 122 123 do { 124 if (irq_pending & 1) 125 generic_handle_irq(irq_num); 126 ++irq_num; 127 irq_pending >>= 1; 128 } while (irq_pending); 129 } 130 131 void __init virt_init_IRQ(void) 132 { 133 unsigned int i; 134 135 m68k_setup_irq_controller(&virt_irq_chip, handle_simple_irq, IRQ_USER, 136 NUM_VIRT_SOURCES - IRQ_USER); 137 138 for (i = 0; i < 6; i++) { 139 140 picres[i] = (struct resource) 141 DEFINE_RES_MEM_NAMED(virt_bi_data.pic.mmio + i * 0x1000, 142 0x1000, picname[i]); 143 if (request_resource(&iomem_resource, &picres[i])) { 144 pr_err("Cannot allocate %s resource\n", picname[i]); 145 return; 146 } 147 148 irq_set_chained_handler(virt_bi_data.pic.irq + i, 149 goldfish_pic_irq); 150 } 151 152 if (request_irq(IRQ_AUTO_7, virt_nmi_handler, 0, "NMI", 153 virt_nmi_handler)) 154 pr_err("Couldn't register NMI\n"); 155 } 156