1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/m68k/q40/config.c 4 * 5 * Copyright (C) 1999 Richard Zidlicky 6 * 7 * originally based on: 8 * 9 * linux/bvme/config.c 10 */ 11 12 #include <linux/errno.h> 13 #include <linux/types.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/console.h> 17 #include <linux/linkage.h> 18 #include <linux/init.h> 19 #include <linux/major.h> 20 #include <linux/serial_reg.h> 21 #include <linux/rtc.h> 22 #include <linux/bcd.h> 23 #include <linux/platform_device.h> 24 25 #include <asm/io.h> 26 #include <asm/bootinfo.h> 27 #include <asm/setup.h> 28 #include <asm/irq.h> 29 #include <asm/traps.h> 30 #include <asm/machdep.h> 31 #include <asm/q40_master.h> 32 #include <asm/config.h> 33 34 #include "q40.h" 35 36 static void q40_get_model(char *model); 37 38 static int q40_hwclk(int, struct rtc_time *); 39 static int q40_get_rtc_pll(struct rtc_pll_info *pll); 40 static int q40_set_rtc_pll(struct rtc_pll_info *pll); 41 42 static void q40_mem_console_write(struct console *co, const char *b, 43 unsigned int count); 44 45 extern int ql_ticks; 46 47 static struct console q40_console_driver = { 48 .name = "debug", 49 .write = q40_mem_console_write, 50 .flags = CON_PRINTBUFFER, 51 .index = -1, 52 }; 53 54 55 /* early debugging function:*/ 56 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/ 57 static int _cpleft; 58 59 static void q40_mem_console_write(struct console *co, const char *s, 60 unsigned int count) 61 { 62 const char *p = s; 63 64 if (count < _cpleft) { 65 while (count-- > 0) { 66 *q40_mem_cptr = *p++; 67 q40_mem_cptr += 4; 68 _cpleft--; 69 } 70 } 71 } 72 73 static int __init q40_debug_setup(char *arg) 74 { 75 /* useful for early debugging stages - writes kernel messages into SRAM */ 76 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) { 77 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4; 78 register_console(&q40_console_driver); 79 } 80 return 0; 81 } 82 83 early_param("debug", q40_debug_setup); 84 85 static int halted; 86 87 #ifdef CONFIG_HEARTBEAT 88 static void q40_heartbeat(int on) 89 { 90 if (halted) 91 return; 92 93 if (on) 94 Q40_LED_ON(); 95 else 96 Q40_LED_OFF(); 97 } 98 #endif 99 100 static void q40_reset(void) 101 { 102 halted = 1; 103 pr_info("*******************************************\n" 104 "Called q40_reset : press the RESET button!!\n" 105 "*******************************************\n"); 106 Q40_LED_ON(); 107 while (1) 108 ; 109 } 110 111 static void q40_halt(void) 112 { 113 halted = 1; 114 pr_info("*******************\n" 115 " Called q40_halt\n" 116 "*******************\n"); 117 Q40_LED_ON(); 118 while (1) 119 ; 120 } 121 122 static void q40_get_model(char *model) 123 { 124 sprintf(model, "Q40"); 125 } 126 127 static unsigned int serports[] = 128 { 129 0x3f8,0x2f8,0x3e8,0x2e8,0 130 }; 131 132 static void __init q40_disable_irqs(void) 133 { 134 unsigned i, j; 135 136 j = 0; 137 while ((i = serports[j++])) 138 outb(0, i + UART_IER); 139 master_outb(0, EXT_ENABLE_REG); 140 master_outb(0, KEY_IRQ_ENABLE_REG); 141 } 142 143 void __init config_q40(void) 144 { 145 mach_sched_init = q40_sched_init; 146 147 mach_init_IRQ = q40_init_IRQ; 148 mach_hwclk = q40_hwclk; 149 mach_get_rtc_pll = q40_get_rtc_pll; 150 mach_set_rtc_pll = q40_set_rtc_pll; 151 152 mach_reset = q40_reset; 153 mach_get_model = q40_get_model; 154 155 #if IS_ENABLED(CONFIG_INPUT_M68K_BEEP) 156 mach_beep = q40_mksound; 157 #endif 158 #ifdef CONFIG_HEARTBEAT 159 mach_heartbeat = q40_heartbeat; 160 #endif 161 mach_halt = q40_halt; 162 163 /* disable a few things that SMSQ might have left enabled */ 164 q40_disable_irqs(); 165 } 166 167 168 int __init q40_parse_bootinfo(const struct bi_record *rec) 169 { 170 return 1; 171 } 172 173 /* 174 * Looks like op is non-zero for setting the clock, and zero for 175 * reading the clock. 176 * 177 * struct hwclk_time { 178 * unsigned sec; 0..59 179 * unsigned min; 0..59 180 * unsigned hour; 0..23 181 * unsigned day; 1..31 182 * unsigned mon; 0..11 183 * unsigned year; 00... 184 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set 185 * }; 186 */ 187 188 static int q40_hwclk(int op, struct rtc_time *t) 189 { 190 if (op) { 191 /* Write.... */ 192 Q40_RTC_CTRL |= Q40_RTC_WRITE; 193 194 Q40_RTC_SECS = bin2bcd(t->tm_sec); 195 Q40_RTC_MINS = bin2bcd(t->tm_min); 196 Q40_RTC_HOUR = bin2bcd(t->tm_hour); 197 Q40_RTC_DATE = bin2bcd(t->tm_mday); 198 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1); 199 Q40_RTC_YEAR = bin2bcd(t->tm_year%100); 200 if (t->tm_wday >= 0) 201 Q40_RTC_DOW = bin2bcd(t->tm_wday+1); 202 203 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 204 } else { 205 /* Read.... */ 206 Q40_RTC_CTRL |= Q40_RTC_READ; 207 208 t->tm_year = bcd2bin (Q40_RTC_YEAR); 209 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1; 210 t->tm_mday = bcd2bin (Q40_RTC_DATE); 211 t->tm_hour = bcd2bin (Q40_RTC_HOUR); 212 t->tm_min = bcd2bin (Q40_RTC_MINS); 213 t->tm_sec = bcd2bin (Q40_RTC_SECS); 214 215 Q40_RTC_CTRL &= ~(Q40_RTC_READ); 216 217 if (t->tm_year < 70) 218 t->tm_year += 100; 219 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1; 220 } 221 222 return 0; 223 } 224 225 /* get and set PLL calibration of RTC clock */ 226 #define Q40_RTC_PLL_MASK ((1<<5)-1) 227 #define Q40_RTC_PLL_SIGN (1<<5) 228 229 static int q40_get_rtc_pll(struct rtc_pll_info *pll) 230 { 231 int tmp = Q40_RTC_CTRL; 232 233 pll->pll_ctrl = 0; 234 pll->pll_value = tmp & Q40_RTC_PLL_MASK; 235 if (tmp & Q40_RTC_PLL_SIGN) 236 pll->pll_value = -pll->pll_value; 237 pll->pll_max = 31; 238 pll->pll_min = -31; 239 pll->pll_posmult = 512; 240 pll->pll_negmult = 256; 241 pll->pll_clock = 125829120; 242 243 return 0; 244 } 245 246 static int q40_set_rtc_pll(struct rtc_pll_info *pll) 247 { 248 if (!pll->pll_ctrl) { 249 /* the docs are a bit unclear so I am doublesetting */ 250 /* RTC_WRITE here ... */ 251 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | 252 Q40_RTC_WRITE; 253 Q40_RTC_CTRL |= Q40_RTC_WRITE; 254 Q40_RTC_CTRL = tmp; 255 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 256 return 0; 257 } else 258 return -EINVAL; 259 } 260 261 #define PCIDE_BASE1 0x1f0 262 #define PCIDE_BASE2 0x170 263 #define PCIDE_CTL 0x206 264 265 static const struct resource q40_pata_rsrc_0[] __initconst = { 266 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE1 * 4, 0x38), 267 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE1 + PCIDE_CTL) * 4, 2), 268 DEFINE_RES_IO(PCIDE_BASE1, 8), 269 DEFINE_RES_IO(PCIDE_BASE1 + PCIDE_CTL, 1), 270 DEFINE_RES_IRQ(14), 271 }; 272 273 static const struct resource q40_pata_rsrc_1[] __initconst = { 274 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE2 * 4, 0x38), 275 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE2 + PCIDE_CTL) * 4, 2), 276 DEFINE_RES_IO(PCIDE_BASE2, 8), 277 DEFINE_RES_IO(PCIDE_BASE2 + PCIDE_CTL, 1), 278 DEFINE_RES_IRQ(15), 279 }; 280 281 static __init int q40_platform_init(void) 282 { 283 if (!MACH_IS_Q40) 284 return -ENODEV; 285 286 platform_device_register_simple("q40kbd", -1, NULL, 0); 287 288 platform_device_register_simple("atari-falcon-ide", 0, q40_pata_rsrc_0, 289 ARRAY_SIZE(q40_pata_rsrc_0)); 290 291 platform_device_register_simple("atari-falcon-ide", 1, q40_pata_rsrc_1, 292 ARRAY_SIZE(q40_pata_rsrc_1)); 293 294 return 0; 295 } 296 arch_initcall(q40_platform_init); 297